DS791 Datasheet, PDF (6/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Table 1: I/O Signal Description (Cont’d)
AXI Read Address Channel Signal
P13
S_AXI_ARADDR[C_S_
AXI_ADDR_WIDTH - 1:0]
AXI
I
N/A
P14 S_AXI_ARVALID
AXI
I
N/A
P15 S_AXI_ARREADY
P16
S_AXI_RDATA[C_S_AXI_
DATA_WIDTH -1:0]
AXI
O
0x1
AXI Read Data Channel Signal
AXI
O
0x0
P17 S_AXI_RRESP[1:0]
AXI
O
0x0
P18 S_AXI_RVALID
AXI
O
0x0
P19 S_AXI_RREADY
AXI
I
0x1
CAN Signals
P20 CAN_CLK
CAN
I
P21 CAN_PHY_RX
CAN
I
P22 CAN_PHY_TX
CAN
O
1
P23 IP2Bus_IntrEvent
CAN
O
1
Note: S_AXI_Clk frequency must be greater than or equal to CAN_CLK frequency.
Read address. The read address bus
gives the address of a read transaction.
Read address valid. This signal
indicates, when HIGH, that the read
address and control information is valid
and remains stable until the address
acknowledgement signal,
S_AXI_ARREADY, is high.
Read address ready. This signal
indicates that the slave is ready to accept
an address and associated control
signals.
Read data
Read response. This signal indicates the
status of the read transfer.
“00“- OKAY
“10“- SLVERR
“11“- DECERR
Read valid. This signal indicates that the
required read data is available and the
read transfer can complete.
Read ready. This signal indicates that
the master can accept the read data and
response information.
Oscillator Clock input (max value of 24
MHz)
CAN bus receive signal from PHY
CAN bus transmit signal to PHY
Interrupt line from CAN
Register Bit Ordering
All registers use big-endian bit ordering where bit-0 is MSB and bit-31 is LSB.Table 2 shows the bit ordering.
Table 2: Register Bit Ordering
0
1
2
............................................
29
30
31
MSB
LSB
DS791 June 22, 2011
www.xilinx.com
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Product Specification