DS791 Datasheet, PDF (22/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Table 22: Interrupt Status Register Bit Descriptions (Cont’d)
Read
29
TXFLL
Only
Transmit FIFO Full Interrupt: A ‘1’ indicates that the TX FIFO is
full.
0
The status of the bit is unaffected if write transactions occur on the
Transmit FIFO when it is already full.
This bit can be cleared only by writing to the Interrupt Clear
Register.
30
TXOK⁽¹⁾
Read
Only
Transmission Successful Interrupt: A ‘1’ indicates that a
0
message was transmitted successfully.
This bit can be cleared by writing to the ICR or when ‘0’ is written
to the CEN bit in the SRR.
31
ARBLST
Read Only
Arbitration Lost Interrupt: A ‘1’ indicates that arbitration was lost
0
during message transmission.
This bit can be cleared by writing to the ICR or when ‘0’ is written
to the CEN bit in the SRR.
1. In Loop Back mode, both TXOK and RXOK bits are set. The RXOK bit is set before the TXOK bit.
Interrupt Enable Register
The Interrupt Enable Register (IER) is used to enable interrupt generation. Table 23 shows the bit positions in the
IER and Table 24 provides IER bit descriptions.
Table 23: Interrupt Enable Register Bit Positions
0 — 19
Reserved
20
EWKUP
21
ESLP
22
EBSOFF
23
EERROR
24
ERXNEMP
25
ERXOFLW
26
27
28
29
30
31
ERXUFLW
ERXOK
ETXBFLL
ETXFLL
ETXOK
EARBLST
Table 24: Interrupt Enable Register Bit Descriptions
Bit(s)
Name
Core Access
Default
Value
Description
0–19
Reserved Read/Write
0
Reserved: These bit positions are reserved for future expansion.
Enable Wake up Interrupt: Writes to this bit enable or disable
interrupts when the WKUP bit in the ISR is set.
20
EWKUP
Read/Write
0
‘1’ = Enable interrupt generation if WKUP bit in ISR is set.
‘0’ = Disable interrupt generation if WKUP bit in ISR is set.
Enable Sleep Interrupt: Writes to this bit enable or disable
interrupts when the SLP bit in the ISR is set.
21
ESLP
Read/Write
0
‘1’ = Enable interrupt generation if SLP bit in ISR is set.
‘0’ = Disable interrupt generation if SLP bit in ISR is set.
Enable Bus OFF Interrupt: Writes to this bit enable or disable
interrupts when the BSOFF bit in the ISR is set.
22
EBSOFF Read/Write
0
‘1’ = Enable interrupt generation if BSOFF bit in ISR is set.
‘0’ = Disable interrupt generation if BSOFF bit in ISR is set.
23
EERROR Read/Write
Enable Error Interrupt: Writes to this bit enable or disable
interrupts when the ERROR bit in the ISR is set.
0
‘1’ = Enable interrupt generation if ERROR bit in ISR is set.
‘0’ = Disable interrupt generation if ERROR bit in ISR is set.
DS791 June 22, 2011
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22
Product Specification