DS791 Datasheet, PDF (12/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Interrupts
The CAN IP core uses a hard-vector interrupt mechanism. It has a single interrupt line (IP2Bus_IntrEvent) to
indicate an interrupt. Interrupts are indicated by asserting the IP2Bus_IntrEvent line (transition of the
IP2Bus_IntrEvent line from a logic '0' to a logic '1').
Events such as errors on the bus line, message transmission and reception, FIFO overflows and underflow
conditions can generate interrupts. During power on, the Interrupt line is driven low.
The Interrupt Status Register (ISR) indicates the interrupt status bits. These bits are set and cleared regardless of the
status of the corresponding bit in the Interrupt Enable Register (IER). The IER handles the interrupt-enable
functionality. The clearing of a status bit in the ISR is handled by writing a '1' to the corresponding bit in the
Interrupt Clear Register (ICR).
The following two conditions cause the IP2Bus_IntrEvent line to be asserted:
• If a bit in the ISR is '1' and the corresponding bit in the IER is '1'.
• Changing an IER bit from a '0' to '1'; when the corresponding bit in the ISR is already '1'.
• Two conditions cause the IP2Bus_IntrEvent line to be deasserted:
• Clearing a bit in the ISR that is '1' (by writing a '1' to the corresponding bit in the ICR); provided the
corresponding bit in the IER is '1'.
• Changing an IER bit from '1' to '0'; when the corresponding bit in the ISR is '1'.
When both deassertion and assertion conditions occur simultaneously, the IP2Bus_IntrEvent line is deasserted
first, and is reasserted if the assertion condition remains true.
DS791 June 22, 2011
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Product Specification