DS791 Datasheet, PDF (4/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
The propagation segment and phase segment 1 are joined and called 'time segment1' (TS1), while phase segment 2
is called 'time segment2' (TS2). The number of time quanta in TS1 and TS2 vary with different networks and are
specified in the Bit Timing Register (BTR), which is passed to the BTL module. The Sync segment is always one time
quantum long.
The BTL state machine runs on the quantum clock. During the SOF bit of every CAN frame, the state machine is
instructed by the Bit Stream Processor module to perform a hard sync, forcing the recessive (r) to dominant edge (d)
to lie in the sync segment. During the rest of the recessive-to-dominant edges in the CAN frame, the BTL is
prompted to perform resynchronization.
During resynchronization, the BTL waits for a recessive-to-dominant edge and after that occurs, it calculates the
time difference (number of tqs) between the edge and the nearest sync segment. To compensate for this time
difference and to force the sampling point to occur at the correct instant in the CAN bit time, the BTL modifies the
length of phase segment 1 or phase segment 2.
The maximum amount by which the phase segments can be modified is dictated by the Synchronization Jump
Width (SJW) parameter, which is also passed to the BTL through the BTR. The length of the bit time of subsequent
CAN bits are unaffected by this process. This synchronization process corrects for propagation delays and oscillator
mismatches between the transmitting and receiving nodes.
After the controller is synchronized to the bus, the state machine waits for a time period of TS1 and then samples the
bus, generating a digital '0' or '1'. This is passed on to the BSP module for higher level tasks.
Bit Stream Processor
The Bit Stream Processor (BSP) module performs several MAC/LLC functions during reception (RX) and
transmission (TX) of CAN messages. The BSP receives a message for transmission from either the TX FIFO or the TX
HPB and performs the following functions before passing the bitstream to BTL.
• Serializing the message
• Inserting stuff bits, CRC bits, and other protocol defined fields during transmission
During transmission, the BSP simultaneously monitors RX data and performs bus arbitration tasks. It then
transmits the complete frame when arbitration is won, and retrying when arbitration is lost.
During reception, the BSP removes Stuff bits, CRC bits, and other protocol fields from the received bitstream. The
BSP state machine also analyses bus traffic during transmission and reception for Form, CRC, ACK, Stuff, and Bit
violations. The state machine then performs error signaling and error confinement tasks. The CAN controller does
not voluntarily generate overload frames but does respond to overload flags detected on the bus.
This module determines the error state of the CAN controller: Error Active, Error Passive, or Bus-off. When TX or
RX errors are observed on the bus, the BSP updates the transmit and receive error counters according to the rules
defined in the CAN 2.0 A, CAN 2.0 B and ISO 11898-1 standards. Based on the values of these counters, the error
state of the CAN controller is updated by the BSP.
DS791 June 22, 2011
www.xilinx.com
4
Product Specification