DS791 Datasheet, PDF (15/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Table 7: Software Reset Register Bit Position
0 — 29
30
31
Reserved
CEN
SRST
Table 8: Software Reset Register Bit Description
Bit(s) Name
Core
Access
Default
Value
Description
0–29 Reserved Read/Write
0
Reserved: These bit positions are reserved for future expansion.
CAN Enable: The Enable bit for the CAN controller.
30
CEN Read/Write
0
'1' = The CAN controller is in Loop Back, Sleep, or Normal mode depending
on the LBACK and SLEEP bits in the MSR.
'0' = The CAN controller is in the Configuration mode.
31
SRST Read/Write
Reset: The Software reset bit for the CAN controller.
0
'1' = CAN controller is reset.
If a '1' is written to this bit, all the CAN controller configuration registers
(including the SRR) are reset. Reads to this bit always return a '0.'
Mode Select Register
Writing to the Mode Select Register (MSR) enables the CAN controller to enter Sleep, Loop Back, or Normal modes.
In Normal mode, the CAN controller participates in normal bus communication. If the SLEEP bit is set to '1’, the
CAN controller enters Sleep mode. If the LBACK bit is set to '1’, the CAN controller enters Loop Back mode.
The LBACK and SLEEP bits should never both be '1' at the same time. At any given point the CAN controller can
be either in Loop Back mode or Sleep mode, but not at the same time. If both are set, the LBACK Mode takes
priority.
Table 9 shows the bit positions in the MSR and Table 10 provides MSR bit descriptions
Table 9: Model Select Register Bit Positions
0 — 29
Reserved
30
LBACK
31
SLEEP
DS791 June 22, 2011
www.xilinx.com
15
Product Specification