DS791 Datasheet, PDF (13/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Configuration Register Descriptions
Table 6 lists the CAN controller configuration registers. Each register is 32-bits wide and is represented in big
endian format. Any read operations to reserved bits or bits that are not used return '0’. ‘0’s are written to reserved
bits and bit fields that are not used. Writes to reserved locations are ignored
Table 6: Configuration Registers
Register Name
AXI Address
(offset from C_S_AXI_BASEADDR)
Access
Control Registers
Software Reset Register (SRR)
Mode Select Register (MSR)
Transfer Layer Configuration Registers
Baud Rate Prescaler Register (BRPR)
Bit Timing Register (BTR)
Error Indication Registers
Error Counter Register (ECR)
Error Status Register (ESR)
0x000
0x004
0x008
0x00C
0x010
0x014
CAN Status Registers
Read/Write
Read/Write
Read/Write
Read/Write
Read
Read/Write to Clear
Status Register (SR)
Interrupt Registers
Interrupt Status Register (ISR)
Interrupt Enable Register (IER)
Interrupt Clear Register (ICR)
Reserved Locations
0x018
Reserved
0x01C
0x020
0x024
0x028 to 0x02C
Read
Read
Read/Write
Write
Reads Return 0/
Write has no affect
Messages
ID
DLC
Data Word 1
Data Word 2
Transmit Message FIFO (TX FIFO)
0x030
0x034
0x038
0x03C
Write
Write
Write
Write
Transmit High Priority Buffer (TX HPB)
ID
DLC
Data Word 1
Data Word 2
0x040
0x044
0x048
0x04C
Write
Write
Write
Write
DS791 June 22, 2011
www.xilinx.com
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Product Specification