DS791 Datasheet, PDF (25/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Message Transmission and Reception
The following rules apply regarding message transmission and reception:
• A message in the TX High Priority Buffer (TX HPB) has priority over messages in the TX FIFO.
• In case of arbitration loss or errors during the transmission of a message, the CAN controller tries to retransmit
the message. No subsequent message, even a newer, higher priority message is transmitted until the original
message is transmitted without errors or arbitration loss.
• The messages in the TX FIFO, TX HPB and RX FIFO are retained even if the CAN controller enters Bus off state
or Configuration mode.
Message Structure
Each message is 16 bytes. Byte ordering for the CAN message structure is shown in Table 27, Table 28,Table 29, and
Table 30.
Table 27: Message Identifier [IDR]
0 — 10
11
12
13 — 30
31
ID [28..18]
SRR/RTR
IDE
ID[17..0]
RTR
Table 28: Data Length Code [DLCR]
0—3
4 — 31
DLC [3..0]
Reserved
Table 29: Data Word 1 [DW1R]
0—7
8 — 15
DB0[7..0]
DB1[7..0]
16 — 23 24 — 31
DB2[7..0] DB3[7..0]
Table 30: Data Word 2 [DW2R]
0—7
8 — 15
DB4[7..0]
DB5[7..0]
16 — 23 24 — 31
DB6[7..0] DB7[7..0]
All 16 bytes must be read from the RX FIFO to receive the complete message. The first word read (4 bytes) returns
the identifier of the received message (IDR). The second read returns the Data Length Code (DLC) field of the
received message (DLCR). The third read returns Data Word 1 (DW1R), and the fourth read returns Data Word 2
(DW2R).
All four words have to be read for each message, even if the message contains less than 8 data bytes. Write
transactions to the RX FIFO are ignored. Reads from an empty RX FIFO return invalid data.
DS791 June 22, 2011
www.xilinx.com
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Product Specification