DS791 Datasheet, PDF (35/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Writing a Message to the TX HPB
All messages written to the TX FIFO should follow the format described in Message Storage, page 24.
To write a message to the TX HPB:
1. Poll the TXBFLL bit in the SR.
The message can be written into the TX HPB when the TXBFLL bit is '0'.
2. Write the ID of the message to the TX HPB ID memory location (0x040).
3. Write the DLC of the message to the TX HPB DLC memory location (0x044).
4. Write Data Word 1 of the message to the TX HPB DW1 memory location (0x048).
5. Write Data Word 2 of the message to the TX HPB DW2 memory location (0x04C).
After each write to the TX HPB, the TXBFLL bit in the Status Register and the TXBFLL bit in the Interrupt Status
Register are set.
Receiving a Message
Whenever a new message is received and written into the RX FIFO, the RXNEMP bit and the RXOK bits in the ISR
are set. In case of a read operation on an empty RX FIFO, the RXUFLW bit in the ISR is set.
Reading a Message from the RX FIFO
Perform the following steps to read a message from the RX FIFO.
1. Poll the RXOK or RXNEMP bits in the ISR. In interrupt mode, the reads can occur after the RXOK or RXNEMP
bits in the ISR generate an interrupt.
a. Read from the RX FIFO memory locations. All the locations must be read regardless of the number of data
bytes in the message.
b. Read from the RX FIFO ID location (0x050)
c. Read from the RX FIFO DLC location (0x054)
d. Read from the RX FIFO DW1 location (0x058)
e. Read from the RX FIFO DW2 location (0x05C)
2. After performing the read, if there are one or more messages in the RX FIFO, the RXNEMP bit in the ISR is set.
This bit can either be polled or can generate an interrupt.
3. Repeat until the FIFO is empty.
Extra Design Consideration
The AXI CAN cores requires an input register on the RX line to avoid a potential error condition where multiple
registers receive different values resulting in error frames. This error condition is rare; however, the work-around
should be implemented in all cases. To work around this issue, insert a register on the RX line clocked by CAN_CLK
with an initial value of '1'. This applies to all versions of the AXI CAN cores.
DS791 June 22, 2011
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