DS791 Datasheet, PDF (23/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Table 24: Interrupt Enable Register Bit Descriptions (Cont’d)
24
ERXNEMP Read/Write
Enable Receive FIFO Not Empty Interrupt: Writes to this bit
enable or disable interrupts when the RXNEMP bit in the ISR is
0
set.
‘1’ = Enable interrupt generation if RXNEMP bit in ISR is set.
‘0’ = Disable interrupt generation if RXNEMP bit in ISR is set.
25
ERXOFLW Read/Write
Enable RX FIFO Overflow Interrupt: Writes to this bit enable or
disable interrupts when the RXOFLW bit in the ISR is set.
0
‘1’ = Enable interrupt generation if RXOFLW bit in ISR is set.
‘0’ = Disable interrupt generation if RXOFLW bit in ISR is set.
26
ERXUFLW Read/Write
Enable RX FIFO Underflow Interrupt: Writes to this bit enable
or disable interrupts when the RXUFLW bit in the ISR is set.
0
‘1’ = Enable interrupt generation if RXUFLW bit in ISR is set.
‘0’ = Disable interrupt generation if RXUFLW bit in ISR is set.
Enable New Message Received Interrupt: Writes to this bit
enable or disable interrupts when the RXOK bit in the ISR is set.
27
ERXOK
Read/Write
0
‘1’ = Enable interrupt generation if RXOK bit in ISR is set.
‘0’ = Disable interrupt generation if RXOK bit in ISR is set.
28
ETXBFLL Read/Write
Enable High Priority Transmit Buffer Full Interrupt: Writes to
this bit enable or disable interrupts when the TXBFLL bit in the
0
ISR is set.
‘1’ = Enable interrupt generation if TXBFLL bit in ISR is set.
‘0’ = Disable interrupt generation if TXBFLL bit in ISR is set.
Enable Transmit FIFO Full Interrupt: Writes to this bit enable
or disable interrupts when TXFLL bit in the ISR is set.
29
ETXFLL
Read/Write
0
‘1’ = Enable interrupt generation if TXFLL bit in ISR is set.
‘0’ = Disable interrupt generation if TXFLL bit in ISR is set.
Enable Transmission Successful Interrupt: Writes to this bit
enable or disable interrupts when the TXOK bit in the ISR is set.
30
ETXOK
Read/Write
0
‘1’ = Enable interrupt generation if TXOK bit in ISR is set.
‘0’ = Disable interrupt generation if TXOK bit in ISR is set.
31
EARBLST Read/Write
Enable Arbitration Lost Interrupt: Writes to this bit enable or
disable interrupts when the ARBLST bit in the ISR is set.
0
‘1’ = Enable interrupt generation if ARBLST bit in ISR is set.
‘0’ = Disable interrupt generation if ARBLST bit in ISR is set.
Interrupt Clear Register
The Interrupt Clear Register (ICR) is used to clear interrupt status bits. Table 25 shows the bit positions in the ICR
and Table 26 gives the ICR bit descriptions.
Table 25: Interrupt Clear Register Bit Positions
0 — 19
20
21
22
Reserved
CWKUP
CSLP
CBSOFF
26
27
28
29
CRXUFLW
CRXOK
CTXBFLL
CTXFLL
23
CERROR
30
CTXOK
24
CRXNEMP
31
CARBLST
25
CRXOFLW
DS791 June 22, 2011
www.xilinx.com
23
Product Specification