DS791 Datasheet, PDF (34/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Programming the Configuration Registers
The following are steps to configure the core when the core is powered-on, or after system or software reset.
1. Choose the operation mode.
a. For Loop Back mode, write a '1' to the LBACK bit in the MSR and '0' to the SLEEP bit in the MSR.
b. For Sleep mode, write a '1' to the SLEEP bit in the MSR and '0' to the LBACK bit in the MSR.
c. For Normal Mode, write '0's to the LBACK and SLEEP bits in the MSR.
2. Configure the Transfer Layer Configuration Registers.
a. Program the Baud Rate Prescalar Register and the Bit Timing Register to correspond to the network timing
parameters and the network characteristics of the system.
3. Configure the Acceptance Filter Registers.
The number of Acceptance Filter Mask and Acceptance Filter ID Register pairs is chosen at build time. To
configure these registers do the following:
a. Write a '0' to the UAF bit in the AFR register corresponding to the Acceptance Filter Mask and ID Register
pair to be configured.
b. Wait until the ACFBSY bit in the SR is '0'.
c. Write the appropriate mask information to the Acceptance Filter Mask Register.
d. Write the appropriate ID information to the to the Acceptance Filter ID Register.
e. Write a '1' to the UAF bit corresponding to the Acceptance Filter Mask and ID Register pair.
f. Repeat the preceding steps for each Acceptance Filter Mask and ID Register pair.
4. Write to the Interrupt Enable Register to choose the bits in the Interrupt Status Register than can generate an
interrupt.
5. Enable the CAN controller by writing a '1' to the CEN bit in the SRR register.
Transmitting a Message
A message to be transmitted can be written to either the TX FIFO or the TX HPB. A message in the TX HPB gets
priority over the messages in the TX FIFO. The TXOK bit in the ISR is set after the CAN core successfully transmits
a message.
Writing a Message to the TX FIFO
All messages written to the TX FIFO should follow the format described in Message Storage, page 24.
To perform a write:
1. Poll the TXFLL bit in the SR. The message can be written into the TX FIFO when the TXFLL bit is '0'
2. Write the ID of the message to the TX FIFO ID memory location (0x030).
3. Write the DLC of the message to the TX FIFO DLC memory location (0x034).
4. Write Data Word 1 of the message to the TX FIFO DW1 memory location (0x038).
5. Write Data Word 2 of the message to the TX FIFO DW2 memory location (0x03C).
Messages can be continuously written to the TX FIFO until the TX FIFO is full. When the TX FIFO is full, the TXFLL
bit in the ISR and the TXFLL bit in the SR are set. If polling, the TXFLL bit in the Status Register should be polled
after each write. If using interrupt mode, writes can continue until the TXFLL bit in the ISR generates an interrupt.
DS791 June 22, 2011
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Product Specification