DS791 Datasheet, PDF (14/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Table 6: Configuration Registers
Receive Message FIFO (RX FIFO)
ID
0x050
DLC
0x054
Data Word 1
0x058
Data Word 2
0x05C
Acceptance Filtering
Acceptance Filter Register (AFR)
0x060
Acceptance Filter Mask Register 1 (AFMR1)
0x064
Acceptance Filter ID Register 1 (AFIR1)
0x068
Acceptance Filter Mask Register 2(AFMR2)
0x06C
Acceptance Filter ID Register 2 (AFIR2)
0x070
Acceptance Filter Mask Register 3(AFMR3)
0x074
Acceptance Filter ID Register 3 (AFIR3)
0x078
Acceptance Filter Mask Register 4(AFMR4)
0x07C
Acceptance Filter ID Register 4 (AFIR4)
0x080
Reserved
Reserved Locations
0x084 to 0x0FC
Read
Read
Read
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Reads Return 0/
Write has no affect
Control Registers
Software Reset Register
Writing ‘1’ to the Software Reset Register (SRR) places the CAN controller in Configuration mode. When in
Configuration mode, the CAN controller drives recessive on the bus line and does not transmit or receive messages.
During power-up, the CEN and SRST bits are '0' and the CONFIG bit in the Status Register (SR) is '1'. The Transfer
Layer Configuration Registers can be changed only when the CEN bit in the SRR Register is '0.'
Use these steps to configure the CAN controller at power up:
1. Configure the Transfer Layer Configuration Registers (BRPR and BTR) with the values calculated for the
specific bit rate.
See Baud Rate Prescaler Register and Bit Timing Register for more information.
2. Do one of the following:
a. For Loop Back mode, write '1' to the LBACK bit in the MSR.
a. For Sleep mode, write '1' to the SLEEP bit in the MSR.
See Operational Modes, page 8 for information about operational modes.
3. Set the CEN bit in the SRR to 1.
After the occurrence of 11 consecutive recessive bits, the CAN controller clears the CONFIG bit in the Status
Register to '0', and sets the appropriate Status bit in the Status Register.
Table 7 shows the bit positions in the SR register and Table 8 provides the Software Reset Register bit descriptions.
DS791 June 22, 2011
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Product Specification