DS791 Datasheet, PDF (10/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Sleep Mode
The CAN controller enters Sleep mode from Configuration mode when the LBACK bit in MSR is '0’, the SLEEP bit
in MSR is '1’, and the CEN bit in SRR is '1’. The CAN controller enters Sleep mode only when there are no pending
transmission requests from either the TX FIFO or the TX High Priority Buffer.
The CAN controller enters Sleep mode from Normal mode only when the SLEEP bit is '1’, the CAN bus is idle, and
there are no pending transmission requests from either the TX FIFO or TX High Priority Buffer.
When another node transmits a message, the CAN controller receives the transmitted message and exits Sleep
mode. When the controller is in Sleep mode, if there are new transmission requests from either the TX FIFO or the
TX High Priority Buffer, these requests are serviced, and the CAN controller exits Sleep mode. Interrupts are
generated when the CAN controller enters Sleep mode or wakes up from Sleep mode.
The CAN controller can enter either Configuration or Normal modes from Sleep mode.
The CAN controller can enter Configuration mode when any configuration condition is satisfied. The CAN
controller enters Normal mode upon the following conditions (wake-up conditions):
• Whenever the SLEEP bit is set to '0'
• Whenever the SLEEP bit is '1', and bus activity is detected
• Whenever there is a new message in the TX FIFO or the TX High Priority Buffer
Loop Back Mode
In Loop Back mode, the CAN controller transmits a recessive bitstream on to the CAN Bus. Any message that is
transmitted is looped back to the RX line and is acknowledged. The CAN controller receives any message that it
transmits. It does not participate in normal bus communication and does not receive any messages that are
transmitted by other CAN nodes.
This mode is used for diagnostic purposes. When in Loop Back mode, the CAN controller can enter Configuration
mode only. The CAN controller enters Configuration mode when any of the configuration conditions are satisfied.
The CAN controller enters Loop Back mode from the Configuration mode if the LBACK bit in MSR is '1' and the
CEN bit in SRR is '1.'
Clocking and Reset
Clocking
The CAN core has two clocks: CAN_CLK and S_AXI_ACLK. The following conditions apply for clock frequencies:
• CAN_CLK can be 8 to 24 MHz in frequency.
• CAN_CLK and S_AXI_ACLK can be asynchronous or can be clocked from the same source
Either of these clocks can be sourced from external oscillator sources or generated within the FPGA. The oscillator
used for CAN_CLK must be compliant with the oscillator tolerance range given in the ISO 11898 -1, CAN 2.0A, and
CAN 2.0B standards.
S_AXI_ACLK
The user can specify the operating frequency for S_AXI_ACLK. Using a DCM to generate this clock is optional.
S_AXI_ACLK frequency must be greater than or equal to CAN_CLK frequency.
DS791 June 22, 2011
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Product Specification