DS791 Datasheet, PDF (21/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Table 21 shows the bit positions in the ISR and Table 22 provides ISR descriptions.
Table 21: Interrupt Status Register Bit Positions
0 — 19
20
21
22
23
Reserved
WKUP
SLP
BSOFF
ERROR
26
27
28
29
30
RXUFLW
RXOK
TXBFLL
TXFLL
TXOK
24
RXNEMP
31
ARBLST
25
RXOFLW
Table 22: Interrupt Status Register Bit Descriptions
Bit(s)
Name
Core
Access
Default
Value
Description
0–19
Reserved Read/Write
0
Reserved: These bit positions are reserved for future expansion.
20
WKUP
Read
Only
Wake up Interrupt: A ‘1’ indicates that the CAN controller entered
0
Normal mode from Sleep Mode.
This bit can be cleared by writing to the ICR or when ’0’ is written
to the CEN bit in the SRR.
Read
21
SLP
Only
Sleep Interrupt: A ‘1’ indicates that the CAN controller entered
Sleep mode.
0
This bit can be cleared by writing to the ICR or when ‘0’ is written
to the CEN bit in the SRR.
22
BSOFF
Read
Only
Bus Off Interrupt: A ‘1’ indicates that the CAN controller entered
0
the Bus Off state.
This bit can be cleared by writing to the ICR or when ‘0’ is written
to the CEN bit in the SRR.
23
ERROR
Read
Only
Error Interrupt: A ‘1’ indicates that an error occurred during
0
message transmission or reception.
This bit can be cleared by writing to the ICR or when ‘0’ is written
to the CEN bit in the SRR.
24
RXNEMP
Read
Only
Receive FIFO Not Empty Interrupt: A ‘1’ indicates that the
0
Receive FIFO is not empty.
This bit can be cleared only by writing to the ICR.
25
RXOFLW
Read
Only
RX FIFO Overflow Interrupt: A ‘1’ indicates that a message has
been lost. This condition occurs when a new message is being
0
received and the Receive FIFO is Full.
This bit can be cleared by writing to the ICR or when ‘0’ is written
to the CEN bit in the SRR.
26
RXUFLW Read Only
RX FIFO Underflow Interrupt: A ‘1’ indicates that a read
0
operation was attempted on an empty RX FIFO.
This bit can be cleared only by writing to the ICR.
27
RXOK
Read
Only
New Message Received Interrupt: A ‘1’ indicates that a
0
message was received successfully and stored into the RX FIFO.
This bit can be cleared by writing to the ICR or when ‘0’ is written
to the CEN bit in the SRR.
28
TXBFLL
Read
Only
High Priority Transmit Buffer Full Interrupt: A ‘1’ indicates that
the High Priority Transmit Buffer is full.
0
The status of the bit is unaffected if write transactions occur on the
High Priority Transmit Buffer when it is already full.
This bit can be cleared only by writing to the ICR.
DS791 June 22, 2011
www.xilinx.com
21
Product Specification