DS791 Datasheet, PDF (24/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Table 26: Interrupt Clear Register Bit Descriptions
Bit(s)
Name
Core
Access
Default
Value
Description
0–19
Reserved Read/Write
0
Reserved: These bit positions are reserved for future expansion.
20
CWKUP
Write Only
0
Clear Wake up Interrupt: Writing a ‘1’ to this bit clears the WKUP bit
in the ISR
21
CSLP
Write Only
0
Clear Sleep Interrupt: Writing a ‘1’ to this bit clears the SLP bit in the
ISR.
22
CBSOFF
Write Only
0
Clear Bus Off Interrupt: Writing a ‘1’ to this bit clears the BSOFF bit
in the ISR.
23
CERROR
Write Only
0
Clear Error Interrupt: Writing a ‘1’ to this bit clears the ERROR bit in
the ISR.
24
CRXNEMP Write Only
0
Clear Receive FIFO Not Empty Interrupt: Writing a ‘1’ to this bit
clears the RXNEMP bit in the ISR.
25
CRXOFLW Write Only
0
Clear RX FIFO Overflow Interrupt: Writing a ‘1’ to this bit clears the
RXOFLW bit in the ISR.
26
CRXUFLW Write Only
0
Clear RX FIFO Underflow Interrupt: Writing a ‘1’ to this bit clears the
RXUFLW bit in the ISR.
27
CRXOK
Write Only
0
Clear New Message Received Interrupt: Writing a ‘1’ to this bit clears
the RXOK bit in the ISR.
28
CTXBFLL
Write Only
0
Clear High Priority Transmit Buffer Full Interrupt: Writing a ‘1’ to
this bit clears the TXBFLL bit in the ISR.
29
CTXFLL
Write Only
0
Clear Transmit FIFO Full Interrupt: Writing a ‘1’ to this bit clears the
TXFLL bit in the ISR.
30
CTXOK
Write Only
0
Clear Transmission Successful Interrupt: Writing a ‘1’ to this bit
clears the TXOK bit in the ISR.
31
CARBLST Write Only
0
Clear Arbitration Lost Interrupt: Writing a ‘1’ to this bit clears the
ARBLST bit in the ISR.
Message Storage
The CAN controller has a Receive FIFO (RX FIFO) for storing received messages. The RX FIFO depth is configurable
and can store up to 64 messages.
Messages that pass any of the acceptance filters are stored in the RX FIFO. When no acceptance filter has been
selected, all received messages are stored in the RX FIFO.
The CAN controller has a configurable Transmit FIFO (TX FIFO) that can store up to 64 messages. The CAN
controller also has a High Priority Transmit Buffer (TX HPB), with storage for one message. When a higher priority
message needs to be sent, write the message to the High Priority Transmit Buffer. The message in the Transmit
Buffer has priority over messages in the TX FIFO.
DS791 June 22, 2011
www.xilinx.com
24
Product Specification