DS791 Datasheet, PDF (20/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Table 20: Status Register Bit Descriptions
Bit(s)
Name
Core
Access
Default
Value
0—19
Reserved
Read/Write
0
20
ACFBSY
Read Only
0
21
TXFLL
Read Only
0
22
TXBFLL
Read Only
0
Read
28
NORMAL
Only
0
Read
29
SLEEP
Only
0
Read
30
LBACK
Only
0
31
CONFIG
Read Only
1
Description
Reserved: These bit positions are reserved for future expansion.
Acceptance Filter Busy: This bit indicates that the Acceptance
Filter Mask Registers and the Acceptance Filter ID Registers
cannot be written to.
‘1’ = Acceptance Filter Mask Registers and Acceptance Filter ID
Registers cannot be written to.
‘0’ = Acceptance Filter Mask Registers and the Acceptance Filter
ID Registers can be written to.
This bit exists only when the number of acceptance filters is not ‘0’
This bit is set when a ‘0’ is written to any of the valid UAF bits in the
Acceptance Filter Register.
Transmit FIFO Full: Indicates that the TX FIFO is full.
‘1’ = Indicates that the TX FIFO is full.
‘0’ = Indicates that the TX FIFO is not full.
High Priority Transmit Buffer Full: Indicates that the High Priority
Transmit Buffer is full.
‘1’ = Indicates that the High Priority Transmit Buffer is full.
‘0’ = Indicates that the High Priority Transmit Buffer is not full.
Normal Mode: Indicates that the CAN controller is in Normal
Mode.
‘1’ = Indicates that the CAN controller is in Normal Mode.
‘0’ = Indicates that the CAN controller is not in Normal mode.
Sleep Mode: Indicates that the CAN controller is in Sleep mode.
‘1’ = Indicates that the CAN controller is in Sleep mode.
‘0’ = Indicates that the CAN controller is not in Sleep mode.
Loop Back Mode: Indicates that the CAN controller is in Loop
Back mode.
‘1’ = Indicates that the CAN controller is in Loop Back mode.
‘0’ = Indicates that the CAN controller is not in Loop Back mode.
Configuration Mode Indicator: Indicates that the CAN controller
is in Configuration mode.
‘1’ = Indicates that the CAN controller is in Configuration mode.
’0’ = Indicates that the CAN controller is not in Configuration mode.
Interrupt Registers
The CAN controller contains a single interrupt line only, but contains several interrupt conditions. Interrupts are
controlled by the interrupt status, enable, and clear registers.
Interrupt Status Register
The Interrupt Status Register (ISR) contains bits that are set when a specific interrupt condition occurs. If the
corresponding mask bit in the Interrupt Enable Register is set, an interrupt is generated.
Interrupt bits in the ISR can be cleared by writing to the Interrupt Clear Register. For all bits in the ISR, a set
condition takes priority over the clear condition and the bit continues to remain '1'.
DS791 June 22, 2011
www.xilinx.com
20
Product Specification