DS791 Datasheet, PDF (2/46 Pages) Xilinx, Inc – LogiCORE IP AXI Controller

LogiCORE IP AXI Controller Area Network (axi_can) (v1.03.a)
Functional Description
Figure 1 illustrates the high-level architecture of the CAN core. The CAN core requires an external 3.3 V compatible
PHY device. Descriptions of the submodules are given in the following sections.
Configuration Registers
Table 6 defines the configuration registers. This module allows for read and write access to the registers through the
external micro-controller interface.
Transmit and Receive Messages
Separate storage buffers exist for transmit (TX FIFO) and receive (RX FIFO) messages through a FIFO structure. The
depth of each buffer is individually configurable up to a maximum of 64 messages.
Transmit High Priority Buffer
The Transfer High Priority Buffer (TX HPB) provides storage for one transmit message. Messages written on this
buffer have maximum transmit priority. They are queued for transmission immediately after the current
transmission is complete, preempting any message in the TX FIFO.
Acceptance Filters
Acceptance Filters sort incoming messages with the user-defined acceptance mask and ID registers to determine
whether to store messages in the RX FIFO, or to acknowledge and discard them. The number of acceptance filters
can be configured from 0 to 4. Messages passed through acceptance filters are stored in the RX FIFO.
X-Ref Target - Figure 1
MicroBlaze
Processor
AXI4-Lite
IPIF
IPIC
Xilinx CAN Controller
Object Layer
TX
FIFO
TX
HPB
TX
Priority
Logic
Configuration
Registers
Transfer Layer
CAN Protocol
Engine
Bit Stream
Processor
Bit Timing
Module
CAN BUS
TX
CAN
PHY
RX
CAN CLK
RX
FIFO
Acceptance
Filtering
DS791_01_100701
Figure 1: AXI CAN Block Diagram
DS791 June 22, 2011
www.xilinx.com
2
Product Specification