DS570 Datasheet, PDF (8/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Table 3: Parameter-Port Dependencies (Cont’d)
Generic
or Port
Name
Affects
P38
Sl_MWrErr[0 :
C_SPLB_NUM_MASTERS - 1]
-
P39
Sl_MRdErr[0 :
C_SPLB_NUM_MASTERS - 1]
-
P43
Sl_MIRQ[0 :
C_SPLB_NUM_MASTERS - 1]
-
P54 ^{SS_I[0 : C_NUM_SS_BITS - 1]}
-
P55 ^{SS_O[0 : C_NUM_SS_BITS - 1]}
-
Depends
Relationship Description
G8
Width of the Sl_MWrErr varies according to
C_SPLB_NUM_MASTERS
G8
Width of the Sl_MRdErr varies according to
C_SPLB_NUM_MASTERS
G8
Width of the Sl_MIRQ varies according to
C_SPLB_NUM_MASTERS
G13
The number of SS_I pins are generated based on
C_NUM_SS_BITS
G13
The number of SS_O pins are generated based on
C_NUM_SS_BITS
Register Descriptions
The Table 4 gives a summary of the XPS SPI IP Core registers. The Transmit FIFO Occupancy Register and the
Receive FIFO Occupancy Register exists only when C_FIFO_EXIST = 1.
Table 4: XPS SPI IP Core Registers
Base Address +
Offset (hex)
Register Name
Access
Default
Type Value (hex)
Description
XPS SPI IP Core Grouping
C_BASEADDR + 40 SRR
Write
N/A
Software Reset Register
C_BASEADDR + 60 SPICR
R/W
0x180 SPI Control Register
C_BASEADDR + 64 SPISR
Read
0x25
SPI Status Register
C_BASEADDR + 68 SPIDTR
Write
0x0
SPI Data Transmit Register
A single register or a FIFO
C_BASEADDR + 6C SPIDRR
Read
0x0
SPI Data Receive Register
A single register or a FIFO
C_BASEADDR + 70 SPISSR
R/W
No slave is SPI Slave Select Register
selected
C_BASEADDR + 74 SPI Transmit FIFO
Occupancy Register⁽¹⁾
Read
0x0
Transmit FIFO Occupancy Register
C_BASEADDR + 78 SPI Receive FIFO
Occupancy Register⁽²⁾
Read
0x0
Receive FIFO Occupancy Register
Interrupt Controller Grouping
C_BASEADDR + 1C
C_BASEADDR + 20
DGIER
IPISR
R/W
R/TOW⁽²⁾
0x0
Device Global Interrupt Enable Register
0x0
IP Interrupt Status Register
C_BASEADDR + 28 IPIER
R/W
0x0
IP Interrupt Enable Register
Notes:
1. This register does not exist if C_FIFO_EXIST = 0.
2. TOW = Toggle On Write. Writing a 1 to a bit position within the register causes the corresponding bit position in the register to
toggle.
DS570 June 22, 2011
www.xilinx.com
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Product Specification