DS570 Datasheet, PDF (10/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Table 6: SPI Control Register (SPICR) Description (C_BASEADDR + 0x60) (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
Description
Manual Slave
24
Select
Assertion
R/W
Enable
Manual Slave Select Assertion Enable. This bit forces the data in the
slave select register to be asserted on the slave select output anytime the
device is configured as a master and the device is enabled (SPE asserted).
’1’
This bit has no effect on slave operation.
’0’ = Slave select output asserted by master core logic
’1’ = Slave select output follows data in slave select register
25
Rx FIFO
Reset
R/W
Receive FIFO Reset. When written to ’1’, this bit forces a reset of the
Receive FIFO to the empty condition. One PLB clock cycle after reset, this
bit is again set to ’0’.
’0’ _{This bit is unassigned when the XPS SPI IP Core is not configured with}
FIFOs.
’0’ = Receive FIFO normal operation
’1’ = Reset receive FIFO pointer
26
Tx FIFO
Reset
R/W
Transmit FIFO Reset. When written to ’1’, this bit forces a reset of the
Transmit FIFO to the empty condition. One PLB clock cycle after reset, this
bit is again set to ’0’.
’0’ _{This bit is unassigned when the XPS SPI IP Core is not configured with}
FIFOs.
’0’ = Transmit FIFO normal operation
’1’ = Reset transmit FIFO pointer
Clock Phase. Setting this bit selects one of two fundamentally different
27
CPHA
R/W
’0’ ^{transfer formats.}
See XPS SPI IP Core Design Description
Clock Polarity. Setting this bit defines clock polarity.
28
CPOL
R/W
’0’ ’0’ = Active high clock; SCK idles low
’1’ = Active low clock; SCK idles high
Master. Setting this bit configures the SPI device as a master or a slave.
29
Master
R/W
’0’ ’0’ = Slave configuration
’1’ = Master configuration
30
SPE
SPI System Enable. Setting this bit to ’1’ enables the SPI devices as noted
below.
’0’ = SPI system disabled. Both master and slave outputs are in "3-state"
R/W
’0’ and slave inputs ignored
’1’ = SPI system enabled. Master outputs active (e.g. MOSI and SCK in idle
state) and slave outputs will become active if SS becomes asserted.
Master will start transfer when transmit data is available
Local Loopback Mode. Enables local loopback operation and is functional
only in master mode.
’0’ = Normal operation
’1’ = Loopback mode. The transmitter output is internally connected to the
31
LOOP
R/W
’0’ ^{receiver input. The receiver and transmitter operate normally, except that}
received data (from remote slave) is ignored
Note that the interrupt enable bit which resides at this bit position of the
M68HC11 specification resides in the interrupt enable register in this
implementation; see Specification Exceptions
DS570 June 22, 2011
www.xilinx.com
10
Product Specification