DS570 Datasheet, PDF (19/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
XPS SPI IP Core Design Description
SPI Device Features
In addition to the features listed in the Features section, the SPI device also includes the following standard features:
• Three signal in/out (in, out, 3-state) for implementing 3-state SPI device in/outs to support multi-master
configuration within the FPGA.
• Works with N times 8-bit data characters in default configuration. The default mode implements manual
control of the SS output via data written to the SPISSR. This appears directly on the SS output when the master
is enabled. This mode can be used only with external slave devices. In addition, an optional operation where the
SS output is toggled automatically with each 8-bit character transfer by the master device. This can be selected
via a bit in the SPICR for SPI master devices.
• Multi-master environment supported (implemented with 3-state drivers and requires software arbitration for
possible conflict). Please refer <RD Red>SPI in Multi-Master Configuration section.
• Multi-slave environment supported (automatic generation of additional slave select output signals for the
master).
• Supports maximum SPI clock rates up to one-half of the PLB clock rate in master mode and one-fourth of the
PLB clock rate in slave modes, i.e. C_SCK_RATIO = 2 is not supported in Slave Mode (This is due to the
synchronization issue between PLB and SPI clock). It is required to take care of PLB and external clock signal
alignment when this core is configured in slave mode.
• Parameterizable baud rate generator.
• The WCOL flag is not supported as a write collision error as described in the M68HC11 reference manual. The
user must take care of not writing into the transmit register when SPI data transfer is in progress.
• Back to Back transactions are supported, which means there can be multiple byte/half-word/word transfers
taking place without interruption provided the transmit FIFO never gets empty and receive FIFO never gets
full.
• All SPI transfers are full-duplex where an 8-bit data character is transferred from the master to the slave and an
independent 8-bit data character is transferred from the slave to the master. This can be viewed as a circular
16-bit shift register; an 8-bit shift register in the SPI master device and another 8-bit shift register in a SPI slave
device that are connected.
DS570 June 22, 2011
www.xilinx.com
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Product Specification