DS570 Datasheet, PDF (3/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
The XPS SPI IP Core supports continuous transfer mode, wherein when configured as master the transfer continues
till the data is available in transmit register/FIFO. This capability is provided in both manual and automatic slave
select modes.
When XPS SPI IP Core is configured as a slave and if inadvertently its slave select line (SPISEL) goes high (i.e.
in-active state) in between the data element transfer, then the current transfer is aborted. Again if the slave select
line goes low then the aborted data element is transmitted again.
The XPS SPI IP Core permits additional slaves to be added with automatic generation of the required decoding logic
for individual slave select outputs by the master. Additional masters can be added as well. However, means to
detect all possible conflicts are not implemented with this interface standard. To eliminate conflicts, software is
required to arbitrate bus control.
The XPS SPI IP Core can communicate with both off-chip and on-chip masters and slaves. The number of slaves is
limited to 32 by the size of the Slave Select Register. However, the number of slaves and masters will impact the
achievable performance in terms of frequency and resource utilization.
All the SPI and INTR registers are 32-bit wide. The XPS SPI IP Core supports only word access to all SPI and INTR
register modules.
The XPS SPI IP Core modules are described in the sections below.
PLB Interface Module: The PLB Interface Module provides the interface to the PLB V4.6 slave single. The read and
write transactions at the PLB are translated into equivalent IP Interconnect (IPIC) transactions. The register
interfaces of the SPI connect to the IPIC. The PLB Interface Module also provides an address decoding service for
XPS SPI Core.
SPI Register Module: The SPI Register Module includes all memory mapped registers (as shown in Figure 1). It
interfaces to the PLB. It consists of Status Register, Control Register, N-bit Slave Select Register (N  32) and a pair
of Transmit/Receive Registers.
INTR Register Module: The INTR Register Module consists of interrupt related registers namely device global
interrupt enable register (DGIER), IP interrupt enable register (IPIER) and IP interrupt status register (IPISR).
SPI Module: The SPI Module consists of a shift register, a parameterized baud rate generator (BRG) and a control
unit. It provides the SPI interface, including the control logic and initialization logic. It is the heart of core.
Optional FIFOs: The Tx FIFO and Rx FIFO are implemented on both transmit and receive paths when enabled by
the parameter C_FIFO_EXIST. The width of Tx FIFO and Rx FIFO is same and it depends on generic
C_NUM_TRANSFER_BITS. The depth of these FIFO’s is 16, which is FIFO design dependent.
DS570 June 22, 2011
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Product Specification