DS570 Datasheet, PDF (28/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
When the XPS SPI IP Core is configured with FIFOs and a series of consecutive SPI 8-bit/16-bit/32-bit element
transfers are performed, SPISR bits and IPISR do indicate completion of the first and the last SPI transfers with no
indication of intermediate transfers. The only way to monitor when intermediate transfers are completed is to
monitor the receive FIFO occupancy number. There is also an interrupt when the transmit FIFO is half empty,
bit(25) of IPISR. There is another interrupt added (DRR_Not_Empty) to indicate that the receive FIFO has at least
one beat of data.
When the SPI device is configured as a slave, the setting/clearing of the bits discussed above for a master coincides
with the setting/clearing of the master bits for both cases of CPHA = ’0’ and CPHA = ’1’. Recall that for CPHA = ’1’
(i.e. no SCK edge denoting the end of the last clock period) the slave has no way of knowing when the end of the last
SCK period occurs unless an PLB clock period counter was included in the SPI slave device. In the slave mode,
when the master SPI selects the core by asserting Slave Select (SS) line, the Slave_Mode_Select interrupt will be
generated. This bit is added in SPISR, IPISR and IPIER registers.
SPI Registers Flow Description
This section provides information on setting the SPI registers to initiate and complete bus transactions.
SPI master device with or without FIFOs where the slave select vector is asserted manually via SPICR bit(24)
assertion.
This flow permits the transfer of N number of byte/half-word/word by toggling of the slave select vector just once.
This is the default mode of operation. Follow these steps to successfully complete an SPI transaction:
1. Start from proper state including SPI bus arbitration.
2. Configure DGIER and IPIER registers as desired.
3. Configure target slave SPI device as required.
4. Write initial data to master SPIDTR register/FIFO. This assumes that the SPI master is disabled.
5. Insure SPISSR register has all ones.
6. Write configuration data to master SPI device SPICR as desired including setting bit(24) for manual asserting of
SS vector and setting both enable bit and master transfer inhibit bit. This initializes SCK and MOSI but inhibits
transfer.
7. Write to SPISSR to manually assert SS vector.
8. Write the above configuration data to master SPI device SPICR, but clear inhibit bit which starts transfer.
9. Wait for interrupt (typically IPISR bit(27)-DRR_Full) or poll status for completion. Wait time depends on SPI
clock ratio.
10. Set master transaction inhibit bit to service interrupt request. Write new data to master register/FIFOs and
slave device then clear master transaction inhibit bit to continue N 8-bit element transfer. Note that an overrun
of the SPIDRR register/FIFO can occur if the SPIDRR register/FIFOs are not read properly. Also note that SCK
will have stretched idle levels between element transfers (or groups of element transfers if utilizing FIFOs) and
that MOSI can transition at end of a element transfer (or group of transfers) but will be stable at least one-half
SCK period prior to sampling edge of SCK.
11. Repeat previous two steps until all data is transferred.
12. Write all ones to SPISSR or exit manual slave select assert mode to deassert SS vector while SCK and MOSI are
in the idle state.
13. Disable devices as desired.
DS570 June 22, 2011
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Product Specification