DS570 Datasheet, PDF (14/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
is empty is by reading the Tx_Empty status bit in the SPI Status Register or the DTR Empty bit in the Interrupt
Status Register.
The Transmit FIFO Occupancy register is shown in Figure 8, while the specifics of the data format is described in
Table 11.
X-Ref Target - Figure 8
Reserved
Occupancy
Value
0
27 28
31
DS570_08
Figure 8: SPI Transmit FIFO Occupancy Register (C_BASEADDR + 0x74)
Table 11: SPI Transmit FIFO Occupancy Register Description (C_BASEADDR + 0x74)
Bit(s)
Name
Core
Reset
Access Value (hex)
Description
0 - 27
Reserved
N/A
N/A
Reserved
28 - 31 Occupancy Value Read
0
Bit 28 is the MSB. The binary value plus 1 yields the occupancy.
SPI Receive FIFO Occupancy Register (Rx_FIFO_OCY)
The SPI Receive FIFO Occupancy Register is present if and only if XPS SPI IP Core is configured with FIFOs
(C_FIFO_EXIST = 1). If it is present and if the Receive FIFO is not empty, the register contains a four-bit,
right-justified value that is one less than the number of elements in the FIFO (occupancy minus one).
This register is a read only. The effect of a write to it (or of a read when the FIFO is empty) will not affect the register
contents. The write operation is not recommended on this register. The only reliable way to determine that the FIFO
is empty is by reading the Rx_Empty status bit in the SPI Status Register.
The Receive FIFO Occupancy register is shown in Figure 9, while the specifics of the data format is described in
Table 12.
X-Ref Target - Figure 9
Reserved
Occupancy
Value
0
27 28
31
DS570_09
Figure 9: SPI Receive FIFO Occupancy Register (C_BASEADDR + 0x78)
Table 12: SPI Receive FIFO Occupancy Register Description (C_BASEADDR + 0x78)
Bit(s)
Name
Core
Reset
Access Value (hex)
Description
0 - 27
Reserved
N/A
N/A
Reserved
28 - 31 Occupancy Value
Read
0
Bit 28 is the MSB. The binary value plus 1 yields the occupancy.
XPS SPI IP Core Interrupt Register Description
The XPS SPI IP Core has number of distinct interrupts that are sent to the interrupt controller module which is one
of the sub-modules of XPS SPI IP Core. The Interrupt controller module allows each interrupt to be enabled
independently (via the IP interrupt enable register (IPIER)).
DS570 June 22, 2011
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Product Specification