DS570 Datasheet, PDF (26/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
X-Ref Target - Figure 17
0ns
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
SPLB_Clk
PLB_ABus[0:31]
A0
PLB_PAValid
PLB_BE[0:3]
F
PLB_RNW
Sl_addrAck
Sl_rdDBus[24:31]
Dr
Sl_rdAck
IP2Bus_Data[0:7]
Dr
IP2Bus_RdAck
spixfer_done
SCK
Receive_Data[0:7]
MOSI
MISO
SS
SPISEL
Dt(0)
** Dr(0)
Dt(1)
Dr(1)
Dt(2)
Dr(2)
Dt(3)
Dr(3)
Dt(4)
Dr(4)
Dt(5)
Dr(5)
Dt(6)
Dr(6)
Dr(0:7)
Dt(7)
Dr(7)
Legend:
A0: Address of Receive_Data Register
Dt: Transmitted Data
Dr: Received Data
SCK is shown for CPOL = 0
**: Not defined, but normally MSB of previously transmitted character for the same slave
DS570_17
Figure 17: Data Read Cycle on SPI Bus with CPHA = 1 and SPICR(24) = 0 for 8-bit data
SPI Protocol Slave Select Assertion Modes
The SPI protocol is designed to have automatic slaves select assertion and manual slave select assertion which are
described in the following sections. All the SPI transfer formats described in the SPI Clock Phase and Polarity
Control section are valid for both Automatic and Manual slave select assertion mode.
SPI Protocol with Automatic Slave Select Assertion
This section describes the SPI protocol where slave select (SS(N)) is asserted automatically by the SPI master device
(i.e SPICR bit(24) = ’0’).
This is the configuration mode provided to permit transfer of data with automatic toggling of slave select (SS) signal
until all the elements are transferred. In this mode the data in the SPISSR register appears on the SS(N) output when
the new transfer starts. After every byte (or element) transfer the SS(N) output goes to ’1’. The data in SPISSR
register again appears on SS(N) output at the beginning of new transfer. The user does not need to manually control
slave select signal.
SPI Protocol with Manual Slave Select Assertion
This section briefly describes the SPI protocol where slave select (SS(N)) is manually asserted by the user (i.e. SPICR
bit(24) = 1).
This is the configuration mode provided to permit transfers of an arbitrary number of elements without toggling
slave select until all the elements are transferred. In this mode, the data in the SPISSR register appears directly on
the SS(N) output.
As described earlier, SCK must be stable before the assertion of slave select. Therefore, when manual slave select
mode is utilized, the SPI master must be enabled first (SPICR bit(24) = 1) to assert SCK to the idle state prior to
asserting slave select.
DS570 June 22, 2011
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Product Specification