DS570 Datasheet, PDF (37/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
supports this speed), the core should be configured in C_SCK_RATIO = 2 mode (where the PLB is configured
to operate at 100 MHz). Due to limited time availability in the design as well as real SPI slave behavior for data
change, the data in the SPI core will be registered in the middle of each falling edge and next consecutive rising
edge. As per the M68HC11 document, the master should register data on each rising edge of SCK in SPI mode
1 and 3. Please note that the data registering mechanism in case of C_SCK_RATIO =2, follows different pattern
than specified in the standard. Although this is applicable to the data registering mechanism in IP core only. The
SPI core when configured in master mode, changes data on each falling edge and this behavior is as per the
M68HC11 standard.
12. When XPS SPI IP core is configured in the slave mode, the data in the core will be registered on the SCK rising
edge + 1 PLB clock signal. Internally, this data is registered on the next rising edge of PLB. The core changes the
data on the SCK falling edge + PLB clock cycle.
Reference Documents
The following documents contain reference information important to understanding the XPS SPI IP Core design:
1. Motorola M68HC11-Rev. 4.0 Reference Manual
2. Motorola MPC8260 PowerQUICC II™ Users Manual 4/1999 Rev. 0
3. IBM CoreConnect^™ 128-Bit Processor Local Bus, Architectural Specification (v4.6)
4. DS561 PLBV46_Slave_Single
5. Spartan-3AN FPGA In-System Flash User Guide,UG333
Support
Xilinx provides technical support for this LogiCORE product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
Ordering Information
This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx ISE Design Suite Embedded
Edition software under the terms of the Xilinx End User License. The core is generated using the Xilinx ISE
Embedded Edition software (EDK).
Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx Intellectual Property page.
For information on pricing and availability of other Xilinx LogiCORE modules and software, please contact your
local Xilinx sales representative.
DS570 June 22, 2011
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Product Specification