DS570 Datasheet, PDF (4/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Design Parameters
To allow the user to obtain a XPS SPI IP Core that is uniquely tailored for the system, certain features can be
parameterized. Parameterization affords a measure of control over the function, resource usage, and performance
of the actually implemented XPS SPI IP Core. The features that can be parameterized are as shown in Table 1.
Table 1: Design Parameters
Generic Feature/Description
Parameter Name
Allowable Values
System Parameters
Default VHDL
Value Type
Target FPGA family
G1
C_FAMILY
spartan3, aspartan3, spartan3an,
spartan3a, spartan3e, spartan3adsp,
aspartan3e, aspartan3a,
aspartan3adsp, virtex4,
virtex5,virtex5fx, qvirtex4, qrvirtex4,
spartan6, aspartan6, virtex6.virtex6cx
spartan3
string
PLB Parameters
G2
PLB base address
G3
PLB high address
C_BASEADDR
C_HIGHADDR
Valid Address⁽¹⁾
Valid Address⁽¹⁾
None⁽²⁾
None⁽²⁾
std_logic
_vector
std_logic
_vector
G4
PLB least significant
address bus width
C_SPLB_AWIDTH 32
32
integer
G5 PLB data width
G6 Shared bus topology
C_SPLB_DWIDTH
C_SPLB_P2P
32, 64, 128
0 = Shared bus topology⁽³⁾
32
integer
0
integer
G7
PLB master ID bus Width C_SPLB_MID_
WIDTH
log₂(C_SPLB_NUM_
MASTERS) with a minimum value of 1
1
integer
G8
Number of PLB masters C_SPLB_NUM_
MASTERS
1 - 16
1
integer
G9
Width of the slave data C_SPLB_NATIVE_ 32
bus
DWIDTH
32
integer
G10 ^{Burst support}
C_SPLB_SUPPORT 0 = No burst support⁽⁴⁾
_BURSTS
0
integer
XPS SPI IP Core Parameters
G11
Include receive and
transmit FIFOs
C_FIFO_EXIST
0 = FIFOs not included
1 = FIFOs included
G12 ^{SPI clock frequency ratio C_SCK_RATIO}
2⁽⁵⁾, 4, 8, Nx16 for
N = 1, 2, 3....
G13
Total number of slave
select bits
C_NUM_SS_BITS
1 - 32
G14
Select number of transfer C_NUM_TRANSFER 8, 16, 32
bits as 8
_BITS
1
32⁽⁶⁾
1
8
integer
integer
integer
integer
DS570 June 22, 2011
www.xilinx.com
4
Product Specification