DS570 Datasheet, PDF (30/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
6. Write initial data to slave transmit FIFO as required.
7. Write initial data to master transmit FIFO.
8. Write enable bit to master SPICR which starts transfer.
9. Continue writing data to both master and slave FIFOs.
10. Wait for interrupt (typically IPISR bit(27)) or poll status for completion.
11. Read IPISR of both master and slave SPI devices as required.
12. Perform interrupt requests as required.
13. Read SPISR of both master and slave SPI devices as required.
14. Perform actions as required or dictated by SPISR data.
Design Constraints
Timing Constraints
When the core is added in the MHS of XPS build, the timing constraints for the core are taken care at the system
level by the XPS tool.
Design Implementation
Target Technology
The target technology is an FPGA listed in the Supported Device Family field in the LogiCORE IP Facts Table.
Device Utilization and Performance Benchmarks
Core Performance
Since the XPS SPI IP Core will be used with other design modules in the FPGA, the utilization and timing numbers
reported in this section are estimates only. When the XPS SPI IP Core is combined with other designs in the system,
the utilization of FPGA resources and timing of the XPS SPI IP Core design will vary from the results reported here.
The XPS SPI IP Core resource utilization for various parameter combinations measured with the Virtex-4 FPGA as
the target device are detailed in Table 16.
Table 16: Performance and Resource Utilization Benchmarks on the Virtex-4 FPGA (xc4vfx12-ff668-10)
Parameter Values
(Other parameters at default values)
Device Resources
Performance
Slices
Slice Flip-
Flops
LUTs
Fmax (MHz)
0
2
2
8
221
174
304
149
1
2
2
8
290
188
349
149
DS570 June 22, 2011
www.xilinx.com
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Product Specification