DS570 Datasheet, PDF (25/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
The user must ensure that external pull-up or pull-down of external SPI 3-state signals are consistent with the
sink/source capability of the FPGA I/O drivers. Recall that the I/O drivers can be configured for different drive
strengths as well as internal pull-ups.
The 3-state signals for multiple external slaves can be implemented as per system design requirements, but the
external bus must follow the SPI M68HC11 specifications.
CPHA Equals One Transfer Format
With CPHA = ’1’, the first SCK cycle begins with an edge on the SCK line from its inactive level to active level (rising
or falling depending on CPOL) as shown in Figure 16. The timing diagram for an SPI data write cycle is shown in
Figure 16.
X-Ref Target - Figure 16
0ns
100ns
200ns
300ns
400ns
Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SPLB_Clk
PLB_ABus[0:31]
A0
PLB_PAValid
PLB_BE[0:3]
F
PLB_wrDBus[24:31]
Dt
PLB_RNW
Sl_addrAck
Sl_wrDack
Bus2ip_Data[0:7]
Dt
IP2Bus_WrAck
Transmit_Data[0:7]
Dt
transfer_start
SCK
MOSI
MISO
SS
SPISEL
Dt(0) Dt(1) Dt(2)
** ^{Dr(0) Dr(1) Dr(2)}
Dt(3) Dt(4) Dt(5) Dt(6) Dt(7)
Dr(3) Dr(4) Dr(5) Dr(6) Dr(7)
Legend:
A0: Address of Transmit_Data Register
Dt: Transmitted Data
Dr: Received Data
SCK is shown for CPOL = 0
**: Not defined, but normally MSB of previously transmitted character for the same slave
DS570_16
Figure 16: Data Write Cycle on SPI Bus with CPHA = 1 and SPICR(24) = 0 for 8-bit data
The timing diagram for an SPI data read cycle when CPHA = ’1’ is shown in Figure 17. The waveforms are shown
for CPOL = ’0’, LSB First = ’0’, and the value of generic C_SCK_RATIO = 4. All PLB and SPI signals will have same
relation with respect to SPLB_Clk and SCK respectively.
DS570 June 22, 2011
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Product Specification