DS570 Datasheet, PDF (13/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
X-Ref Target - Figure 6
Reserved
Rx Data (D0 - DN-1)
0
31-N 31-N+1
31
DS570_06
Figure 6: SPI Data Receive Register (C_BASEADDR + 0x6C)
Table 9: SPI Data Receive Register (SPIDRR) Description (C_BASEADDR + 0x6C)
Bit(s)
Name
Core Reset
Access Value
Description
0 - [31-N]
Reserved
N/A
N/A Reserved
[31-N+1] - 31
Rx Data^{<RD Red><SP}
Superscript>(1) _{(D0 - DN-1)}
Read
only
N-bit SPI receive data. N can be 8, 16 or 32. The bit postion 31
represents N-1 data bit.
0
N = 8 when C_NUM_TRANSFER_BITS = 8
N = 16 when C_NUM_TRANSFER_BITS = 16
N = 32 when C_NUM_TRANSFER_BITS = 32
Notes:
1. The D_N-1 bit will always represent the MSB bit irrespective of "LSB first" or "MSB first" transfer selection.
SPI Slave Select Register (SPISSR)
This register contains an active-low, one-hot encoded slave select vector SS of length N, where N is the number of
slaves set by parameter C_NUM_SS_BITS. The bits of SS occupy the right-most bits of the register. At most one bit
may be asserted low. This bit denotes the slave with whom the local master will communicate.
The bit assignment in the SPISSR is shown in Figure 7 and described in Table 10.
X-Ref Target - Figure 7
Reserved
Selected Slave
0
31-N 31-N+1
31
DS570_06
Figure 7: SPI Slave Select Register (C_BASEADDR + 0x70)
Table 10: SPI Slave Select Register (SPISSR) Description (C_BASEADDR + 0x70)
Bit(s)
Name
Core Reset
Access Value
Description
0 - [31-N] Reserved
N/A
N/A Reserved
[31-N+1] - 31
Selected
Slave
R/W
Active-low, one-hot encoded slave select vector of length N-bits. N must
be less than or equal to the databus width (32-bit). The slaves are
1
numbered right to left starting at zero with the LSB. The slave numbers
correspond to the indexes
of signal SS.
SPI Transmit FIFO Occupancy Register (Tx_FIFO_OCY)
The SPI Transmit FIFO Occupancy Register is present if and only if XPS SPI IP Core is configured with FIFOs
(C_FIFO_EXIST = 1). If it is present and if the Transmit FIFO is not empty, the register contains a four-bit,
right-justified value that is one less than the number of elements in the FIFO (occupancy minus one).
This register is a read only. The effect of a write to it (or of a read when the FIFO is empty) will not affect the register
contents. The write operation is not recommended on this register. The only reliable way to determine that the FIFO
DS570 June 22, 2011
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Product Specification