DS570 Datasheet, PDF (11/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
SPI Status Register (SPISR)
The SPI Status Register (SPISR) is a read-only register that gives the programmer visibility of the status of some
aspects of the XPS SPI IP Core. The bit assignment in the SPISR is shown in Figure 4 and described in Table 7.
Writing to the SPISR is not recommended and if it is done by mistake, then no change will be there in register
contents.
X-Ref Target - Figure 4
Reserved
Tx_Empty
MODF
Rx_Empty
0
25 26 27 28 29 30 31
Slave_Mode_
Rx_Full
Tx_Full
Select
DS570_04
Figure 4: SPI Status Register (C_BASEADDR + 0x64)
Table 7: SPI Status Register (SPISR) Description (C_BASEADDR + 0x64)
Bit(s)
Name
Core Reset
Access Value
Description
0 - 25 Reserved N/A
N/A
Reserved
26
Slave_Mo
de_Select
Read
Slave_Mode_Select Flag. This flag is asserted when the core is configured in
slave mode. Slave_Mode_Select will be activated as soon as master SPI core
asserts the Chip Select pin for the core.
’1’ _{’1’ = Default}
’0’ = Asserted when core configured in slave mode and selected by external SPI
master
Mode-Fault Error Flag. This flag is set if the SS signal goes active while the
SPI device is configured as a master. MODF is automatically cleared by reading
27
MODF
Read
’0’
the SPISR. MODF does generate an interrupt with a single cycle strobe when
the MODF bit transitions from a low to high.
’0’ = No error
’1’ = Error condition detected
28
Tx_Full
Read
Transmit Full. When a transmit FIFO exists, this bit will be set high when the
’0’
transmit FIFO is full.
When FIFOs don’t exist, this bit is set high when an PLB write to the register
has been made. This bit is cleared when the SPI transfer is completed.
Transmit Empty. When a transmit FIFO exists, this bit will be set high when the
transmit FIFO is empty. The occupancy of the FIFO is decremented with the
29
Tx_
Empty
Read
’1’
completion of each SPI transfer.
When FIFOs don’t exist, this bit is set with the completion of an SPI transfer.
Either with or without FIFOs, this bit is cleared upon a PLB write to the FIFO or
transmit register.
30
Rx_Full Read
Receive Full. When a receive FIFO exists, this bit will be set high when the
receive FIFO is full. The occupancy of the FIFO is incremented with the
’0’ completion of each SPI transaction.
When FIFOs don’t exist, this bit is set high when an SPI transfer has completed.
Rx_Empty and Rx_Full are complements in this case.
Receive Empty. When a receive FIFO exists, this bit will be set high when the
31
Rx_
Empty
Read
receive FIFO is empty. The occupancy of the FIFO is decremented with each
’1’ FIFO read operation.
When FIFOs don’t exist, this bit is set high when the receive register has been
read. This bit is cleared at the end of a successful SPI transfer.
DS570 June 22, 2011
www.xilinx.com
11
Product Specification