DS570 Datasheet, PDF (22/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
A similar error detection mechanism has been implemented for SPI slave devices. The error detected is when a SPI
device configured as a slave but is not enabled and is selected (i.e. its SS bit is asserted) by another SPI device. When
this condition is detected, IPISR bit(30) is set by a strobe to the IPISR register.
Under-run and over-run conditions error detection is provided as well. Under-run conditions can happen only in
slave mode operation. This happens when a master commands a transfer but the slave does not have data in the
transmit register or FIFO for transfer. In this case, the slave under-run interrupt is asserted and the slave shift
register is loaded with all zeros for transmission. Over-run can happen to both master and slave devices where a
transfer occurs when the receive register or FIFO is full. During an over-run condition, the data received in that
transfer is not registered (i.e. it is lost) and the IPISR over-run interrupt bit(26) is asserted.
Precautions to be Taken while Assigning the C_SCK_RATIO Parameter
XPS SPI IP Core is tested in hardware with the SPI slave devices like serial EEPROM’s, ATMEL,
STMicro-Electronics and Intel flash memories. Please read the data sheet of targeted SPI slave flash memory or
EEPROM’s for maximum speed of operation. It is user’s responsibility to mention the correct values while deciding
the PLB clock and selecting the C_SCK_RATIO parameter of the core. The PLB clock and the C_SCK_RATIO will
decide the clock at SCK pin of XPS SPI IP Core. While using different external SPI slave devices, the C_SCK_RATIO
should be set carefully and maximum of the clock supported by all the external SPI slave devices should be taken
into account.
XPS SPI Core Configured in Slave Mode
The XPS SPI core can be configured in the slave mode by connecting the external master’s slave select line to SPISEL
and by setting bit 29 of SPI Control Register (SPICR) to '0'. All the incoming signals are synchronized to the PLB
when C_SCK_RATIO > 4. Due to the tight timing requirements when C_SCK_RATIO = 4 the incoming SCK clock
signal and its synchronized signals are used directly in the internal logic. Therefore it is required that the external
clock be synchronized with the PLB clock when C_SCK_RATIO = 4. For other C_SCK_RATIO values, it is preferred
but may not be necessary to have such synchronization.
During the slave mode operation it is strongly recommended to use the FIFO by setting C_FIFO_EXIST = 1. In the
slave mode, two new interrupts are available in IPISR DRR_Not_Empty - bit 23 and Slave_Mode_Select - bit 24
along with the available interrupts. Before other SPI master starts communication, it is mandatory to fill the slave
core transmit FIFO with the required data beats. Once the master starts communication, with the core configured in
slave mode, the core will transfer data till the data exists in its transmit FIFO. At the end of last data beat transmitted
from slave FIFO, core (in slave mode) will generate DTR Empty signal to notify that new data beats needed to be
filled in its transmit FIFO before further communication started.
When the core is intended to be used in the slave mode, then the user should take care of pre-filling the core’s DTR
FIFO at least for 2 locations. This should be done immediately after POR to avoid any under run interrupt from the
core. The external master clock should be set at higher SPI clock division ratios like 1/64 or more, which will be
useful for the processor to fill the DTR FIFO of core, after receiving the slave mode select interrupt.
SPI IP Core Transfer Formats
SPI Clock Phase and Polarity Control
Software can select any of four combinations of serial clock (SCK) phase and polarity with programmable bits in the
SPICR. The clock polarity (CPOL) bit selects an active high (i.e. the clock’s idle state = low) or active low clock (i.e.
DS570 June 22, 2011
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Product Specification