DS570 Datasheet, PDF (17/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Table 14: IP Interrupt Status Register (IPISR) Description (C_BASEADDR + 0x20) (Cont’d)
Bit(s)
Name
Access
Reset
Value
Description
28
DTR Under-
run
R/TOW⁽¹⁾
Data Transmit Register/FIFO Under-run. IPISR bit(28) is the data transmit
register/FIFO under-run interrupt. This bit is set at the end of an SPI element
transfer by a one-clock period strobe to the interrupt register when data is
’0’ requested from an "empty" transmit register/FIFO by the SPI core logic in
order to perform an SPI transfer. This can occur only when the SPI device is
configured as a slave and is enabled, i.e. SPE bit set. All zeros are loaded in
the shift register and transmitted by the slave in an under-run condition.
29 DTR Empty R/TOW⁽¹⁾
Data Transmit Register/FIFO Empty. IPISR bit(29) is the data transmit
register/FIFO empty interrupt. Without FIFOs, this bit is set at the end of an
SPI element transfer by a one-clock period strobe to the interrupt register.
With FIFOs, this bit is set at the end of the SPI element transfer when the
’0’
transmit FIFO is emptied by a one-clock period strobe to the interrupt register.
See section <RD Red>Transfer Ending Period. In the context of the
M68HC11 reference manual, when configured without FIFOs, this interrupt is
equivalent in information content to the complement of SPI transfer complete
flag (SPIF) interrupt bit. In master mode if this bit is set to ’1’ no more SPI
transfers are permitted.
30 Slave MODF R/TOW⁽¹⁾
Slave Mode-Fault Error. IPISR bit(30) is the slave mode-fault error flag. This
’0’
interrupt is generated if the SS signal goes active while the SPI device is
configured as a slave but is not enabled. This bit is set immediately upon SS
going active and continually set if SS is active and the device is not enabled.
Mode-Fault Error. IPISR bit(31) is the mode-fault error flag. This interrupt is
31
MODF
R/TOW⁽¹⁾
’0’ generated if the SS signal goes active while the SPI device is configured as
a master. This bit is set immediately upon SS going active.
Notes:
1. TOW = Toggle On Write. Writing a ’1’ to a bit position within the register causes the corresponding bit position in the register to
toggle.
IP Interrupt Enable Register (IPIER)
The Interrupt controller has a register IPIER that can cause a system level interrupt. This interrupt is generated if the
enabled bit in IPIER detects any activity on corresponding IPISR bit. The IPIER has an enable bit for each defined bit
of the IPISR as shown in Figure 12 and described in Table 15. All bits are cleared upon reset.
X-Ref Target - Figure 12
Reserved
DRR
Full
DRR_Not ^{Tx FIFO}
_Empty ^{Half Empty}
DTR
Empty MODF
0
22 23 24 25 26 27 28 29 30 31
Slave_Select
_Mode
DRR
Over-run
Slave
MODF
DTR
Under-run
DS570_12
Figure 12: IP Interrupt Enable Register (IPIER) (C_BASEADDR + 0x28)
DS570 June 22, 2011
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Product Specification