DS570 Datasheet, PDF (16/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
X-Ref Target - Figure 11
0
Reserved
DRR
DRR_Not _{Tx FIFO} ^Full _DTR
_Empty _{Half Empty}
Empty MODF
22 23 24 25 26 27 28 29 30 31
Slave_Select _DRR
Slave
_Mode
Over-run
MODF
DTR
Under-run
DS570_11
Figure 11: Interrupt Status Register (IPISR) (C_BASEADDR + 0x20)
Table 14: IP Interrupt Status Register (IPISR) Description (C_BASEADDR + 0x20)
Bit(s)
Name
Access
Reset
Value
Description
0 - 22 Reserved
N/A
N/A Reserved
23
DRR_Not_ _R/TOW(1)
Empty
DRR Not Empty.
IPISR bit(23) is the DRR Not Empty bit.
The assertion of this bit is applicable only in case where C_FIFO_EXIST = 1
and the core is configured in slave mode. This bit is set when the DRR FIFO
receives the first data during the SPI transaction. This bit is set by one-clock
’0’ _{period strobe to the interrupt register when the core receives first data beat.}
Please note that assertion of this bit is applicable only when the
C_FIFO_EXIST = 1 and core is configured in slave mode. In C_FIFO_EXIST
= 0 this bit will always return ’0’. So it is recommended to use this bit only in
C_FIFO_EXIST = 1 condition when the core is configured in slave mode. In
master mode, this bit always returns ’0’.
Slave Select Mode.
IPISR bit(24) is the Slave Select Mode bit.
Slave_
The assertion of this bit is applicable only when the core is configured in slave
24
Select_
R/TOW⁽¹⁾
’0’
mode. This bit is set when the other SPI master core selects the core by
asserting the Slave Select line. This bit is set by one-clock period strobe to
Mode
the interrupt register.
Please note that this bit is applicable only when the core is configured in the
slave mode. In master mode, this bit always returns ’0’.
25
Tx FIFO Half
Empty
R/TOW⁽¹⁾
Transmit FIFO Half Empty. IPISR bit(25) is the transmit FIFO half empty
interrupt. This bit is set by a one-clock period strobe to the interrupt register
’0’ ^{when the occupancy value is decremented from "1000" to "0111". Note that}
"0111" means there are 8 elements in the FIFO to be transmitted.
This interrupt exists only if the XPS SPI IP Core is configured with FIFOs.
Data Receive Register/FIFO Over-run. IPISR bit(26) is the data receive
26
DRR
Over-run
R/TOW⁽¹⁾
FIFO over-run interrupt. This bit is set by a one-clock period strobe to the
’0’ interrupt register when an attempt to write data to a full receive register or
FIFO is made by the SPI core logic in order to complete an SPI transfer.
This can occur when the SPI device is in either master or slave mode.
Data Receive Register/FIFO Full. IPISR bit(27) is the data receive register
full interrupt. Without FIFOs, this bit is set at the end of an SPI element (An
element can be a byte, half-word or word depending on the value of
27
DRR Full R/TOW⁽¹⁾
’0’ C_NUM_TRANSFER_BITS generic) transfer by a one-clock period strobe to
the interrupt register. With FIFOs, this bit is set at the end of the SPI element
transfer when the receive FIFO has been filled by a one-clock period strobe
to the interrupt register.
DS570 June 22, 2011
www.xilinx.com
16
Product Specification