DS570 Datasheet, PDF (12/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
SPI Data Transmit Register (SPIDTR)
This register is written with a data to be transmitted on the SPI bus. Once the SPE bit is set to ’1’ in master mode or
SPISEL is active in the slave mode, the data is transferred from the SPIDTR to the shift register.
If a transfer is in progress, the data in the SPIDTR is loaded in the shift register as soon as the data in the shift
register is transferred to the SPIDRR and a new transfer starts. The data is held in the SPIDTR until a subsequent
write overwrites the data. The SPIDTR is shown in Figure 5, while Table 8 shows specifics of the data format.
When a transmit FIFO exists, data is written directly in the FIFO and the first location in the FIFO is treated as the
SPIDTR. The pointer is decremented after completion of each SPI transfer.
This register may not be read and may only be written when it is known that space for the data is available. If an
attempt to write is made on a full register or FIFO, then the PLB write transaction completes with an error condition.
Reading to the SPIDTR is not allowed and the read transaction will result in undefined data.
X-Ref Target - Figure 5
Reserved
Tx Data (D0 - DN-1)
0
31-N 31-N+1
31
DS570_05
Figure 5: SPI Data Transmit Register (C_BASEADDR + 0x68)
Table 8: SPI Data Transmit Register (SPIDTR) Description (C_BASEADDR + 0x68)
Bit(s)
Name
Core Reset
Access Value
Description
0 - [31-N]
Reserved
N/A
N/A Reserved
[31-N+1]
- 31
Tx Data^{<RD Red><SP}
Superscript>(1) _{(D0 -}
D_N-1)
Write
only
N-bit SPI transmit data. N can be 8, 16 or 32. The bit postion 31
represents N-1 data bit.
0 ^{N = 8 when C_NUM_TRANSFER_BITS = 8}
N = 16 when C_NUM_TRANSFER_BITS = 16
N = 32 when C_NUM_TRANSFER_BITS = 32
Notes:
1. The D_N-1 bit will always represent the MSB bit irrespective of "LSB first" or "MSB first" transfer selection.
SPI Data Receive Register (SPIDRR)
This register is used to read data that is received from the SPI bus. This is a double buffered register. The received
data is placed in this register after each complete transfer. The SPI architecture does not provide any means for a
slave to throttle traffic on the bus; consequently, the SPIDRR is updated following each completed transaction only
if the SPIDRR was read prior to the last SPI transfer. If the SPIDRR was not read (i.e. is full), then the most recently
transferred data will be lost and a receive over-run interrupt will occur. The same condition can occur with a master
SPI device as well.
For both master and slave SPI devices with a receive FIFO, the data is buffered in the FIFO. The receive FIFO is a
read only buffer. If an attempt to read an empty receive register or FIFO is made, then the PLB read transaction
completes with an error condition. The effect is undefined if an attempt is made to write the SPIDRR. The write
transaction is not recommended and if it does so then will not affect the register contents. The SPIDRR is shown in
Figure 6, while the specifics of the data format is described in Table 9.
DS570 June 22, 2011
www.xilinx.com
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Product Specification