DS570 Datasheet, PDF (2/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Functional Description
The top level block diagram for the XPS SPI IP Core is shown in Figure 1..
X-Ref Target - Figure 1
PLB
PLB
Interface
Module
SPI REGISTER
MODULE
Status Register
(SPISR)
Control Register
(SPICR)
Slave Select Register
(SPISSR)
Transmit Register
(SPIDTR)
Receive Register
(SPIDRR)
Tx FIFO ⁽¹⁾
Rx FIFO ⁽¹⁾
SPI MODULE
BRG ⁽³⁾
INTR REGISTER
MODULE
Global Interrupt Enable
Register (DGIER)
IP Interrupt Status
Register (IPISR)
IP Interrupt Enable
Register (IPIER)
Control Unit
SPI
Ports
SCK_I
SCK_O
SCK_T
MISO_I
MISO_O
MISO_T
MOSI_I
MOSI_O
MOSI_T
(2)
SS
SPISEL
1 = The width of Tx FIFO, Rx FIFO and *Shift Register depends on
the value of generic C_NUM_TRANSFER_BITS.
2 = The width of SS depends on the value of generic C_NUM_SS_BITS
3 = BRG stands for Baud Rate Generator
Figure 1: Top-Level Block Diagram for the XPS SPI IP Core
DS570_01
The XPS SPI IP Core is a full-duplex synchronous channel that supports four-wire interface (receive, transmit, clock
and slave-select) between a master and a selected slave.
The XPS SPI IP Core supports Manual Slave Select Mode as the Default Mode of operation. This mode allows the
user to manually control the slave select line by the data written to the slave select register. This allows transfers of
an arbitrary number of elements without toggling the slave select line between elements. However, the user must
toggle the slave select line before starting a new transfer.
The other mode of operation is Automatic Slave Select Mode. In this mode the slave select line is toggled
automatically after each element transfer. See SPI Protocol with Automatic Slave Select Assertion for more details.
DS570 June 22, 2011
www.xilinx.com
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Product Specification