DS570 Datasheet, PDF (24/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Signal SCK remains in the idle state until one-half period following the assertion of the slave select line which
denotes the start of a transaction. Since assertion of the SS(N) line denotes the start of a transfer, it must be
de-asserted and re-asserted for sequential element transfers to the same slave device.
One bit of data is transferred per SCK clock period. Data is shifted on one edge of SCK and is sampled on the
opposite edge when the data is stable. Consistent with the M68HC11 SPI specification, selection of clock polarity
and a choice of two different clocking protocols on an 8-bit/16-bit/32-bit oriented data transfer is possible via bits
in the SPICR.
The MOSI and MISO ports behave differently depending on whether the SPI device is configured as a master or a
slave. When configured as a master, the MOSI port is a serial data output port and the MISO is a serial data input
port. The opposite is true when the device is configured as a slave; the MISO port is a slave serial data output port
and the MOSI is a serial data input port. There may be only one master and one slave transmitting data at any given
time. The bus architecture provides limited contention error detection (i.e. multiple devices driving the shared
MISO and MOSI signals) and requires the software to provide arbitration to prevent possible contention errors.
X-Ref Target - Figure 15
0ns
50ns
100ns
150ns
200ns
250ns
300ns
350ns
400ns
Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
SPLB_Clk
PLB_ABus[0:31]
A0
PLB_PAValid
PLB_BE[0:3]
F
PLB_RNW
Sl_addrAck
Sl_rdDBus[24:31]
Dr
Sl_rdAck
IP2Bus_Data[0:7]
Dr
IP2Bus_RdAck
spixfer_done
SCK
Receive_Data[0:7]
MOSI
MISO
SS
SPISEL
Dt(0)
Dr(0)
Dt(1)
Dr(1)
Dt(2)
Dr(2)
Dt(3)
Dr(3)
Dt(4)
Dr(4)
Dt(5)
Dr(5)
Dt(6)
Dr(6)
Dt(7)
Dr(7)
Dr(0:7)
**
Legend:
A0: Address of Receive_Data Register
Dt: Transmitted Data
Dr: Received Data
SCK is shown for CPOL = 0
**: Not defined, but normally MSB of character just received
DS570_15
Figure 15: Data Read Cycle on SPI Bus with CPHA = 0 and SPICR(24) = 0 for 8-bit data
All SCK, MOSI, and MISO pins of all devices are respectively hardwired together. For all transactions, a single SPI
device is configured as a master and all other SPI devices on the SPI bus are configured as slaves.
The single master drives the SCK and MOSI pins to the SCK and MOSI pins of the slaves. The uniquely selected
slave device drives data out from its MISO pin to the MISO master pin, thus realizing full-duplex communication.
The Nth bit of the SS(N) signal selects the Nth SPI slave with an active-low signal. All other slave devices ignore
both SCK and MOSI signals. In addition, the non-selected slaves (i.e. SS pin high) drive their MISO pin to 3-state so
as not to interfere with SPI bus activities.
When external slave SPI devices are implemented, SCK, MOSI and MISO, as well as the needed SS(N) signals, are
brought out to pins. All signals are true 3-state bus signals and erroneous external bus activity can corrupt internal
transfers when both internal and external devices are present.
DS570 June 22, 2011
www.xilinx.com
24
Product Specification