DS570 Datasheet, PDF (15/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
The interrupt registers are in the interrupt module. The XPS SPI IP Core permits multiple conditions for an
interrupt, or an interrupt strobe which occurs only after the completion of a transfer.
Setting the parameter C_FIFO_EXIST = 1 makes available almost all the interrupts shown in Table 14 when the core
is configured in the master mode.
Setting the parameter C_FIFO_EXIST=0 will disable the interrupt for Tx FIFO Half Empty and DRR Not
Empty,(bit(25) and bit (23) respectively) of IPISR and IPIER. Writing to these bits will not have any effect and
reading these bits will return zero.
Device Global Interrupt Enable Register (DGIER)
The Device Global Interrupt Enable Register is used to globally enable the final interrupt output from the Interrupt
controller as shown in Figure 10 and described in Table 13. This bit is a read/write bit and is cleared upon reset.
X-Ref Target - Figure 10
Reserved
01
31
DS570_10
Figure 10: Device Global Interrupt Enable Register (DGIER) (C_BASEADDR + 0x1C)
Table 13: Device Global Interrupt Enable Register(DGIER) Description (C_BASEADDR + 0x1C)
Bit(s)
Name
Access
Reset
Value
Description
Global Interrupt Enable. It enables all individually enabled interrupts to be
0
GIE
R/W
’0’
passed to the interrupt controller.
’0’ = Disabled
’1’ = Enabled
1 - 31 Reserved
N/A
N/A Reserved
IP Interrupt Status Register (IPISR)
Up to nine unique interrupt conditions are possible depending upon whether the system is configured with FIFOs
or not as well as if configured in master mode or slave mode. A system without FIFOs has seven interrupts.
The interrupt controller has 32-bit Interrupt Status Register. This register collects all the interrupts events based
upon the activity on the individual bits (applicable bits). These bits assignment in the Interrupt register for a 32-bit
data bus is shown in Figure 11 and described in Table 14. Setting of the bits of this register is depend only upon the
activities on the corresponding bit. The interrupt register is a read/toggle on write register and by writing a ’1’ to a
bit position within the register causes the corresponding bit position in the register to ’toggle’. All register bits are
cleared upon reset.
DS570 June 22, 2011
www.xilinx.com
15
Product Specification