DS570 Datasheet, PDF (20/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
SPI in Multi-Master Configuration
The SPI bus to a given slave device (N-th device) consists of four wires, Serial Clock (SCK), Master Out Slave In
(MOSI), Master In Slave Out (MISO) and Slave Select (SS(N)). The signals SCK, MOSI and MISO are shared for all
slaves and masters.
X-Ref Target - Figure 13
SPI Device 0
MOSI
MISO
SCK
SPISEL
SS(1)
SS(2)
SS(3)
SS(0)
SS(1)
SS(2)
SS(3)
SPI Device 1
MOSI
MISO
SCK
SPISEL
SS(1)
SS(2)
SS(3)
SPI Device 2
MOSI
MISO
SCK
SPISEL
SS(1)
SS(2)
SS(3)
SPI Device 3
MOSI
MISO
SCK
SPISEL
SS(1)
SS(2)
SS(3)
Slave only devices, which are not shown,
have only SPISEL local slave select port
and do not have SS(N) remote slave select port.
DS570_13
Figure 13: Multi-Master Configuration Block Diagram
Each master SPI device has the functionality to generate an active-low, one-hot encoded SS(N) vector where each bit
is assigned an SS signal for each slave SPI device. It is possible for SPI master/slave devices to be both internal to the
FPGA and SPI slave devices to be external to the FPGA. SPI pins will be automatically generated through Xilinx
Platform Generator when interfacing to an external SPI slave device. Multiple SPI master/slave devices are shown
in Figure 13.
Optional FIFOs
The user has the option to include FIFOs in the XPS SPI IP Core as shown in Figure 1. Since SPI is full-duplex, both
transmit and receive FIFOs are instantiated as a pair.
When FIFOs are implemented, the slave select address is required to be the same for all data buffered in the FIFOs.
This is required because a FIFO for the slave select address is not implemented. Both transmit and receive FIFOs are
16 elements deep and are accessed via single PLB transactions since burst mode is not supported.
DS570 June 22, 2011
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Product Specification