DS570 Datasheet, PDF (5/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Table 1: Design Parameters (Cont’d)
Generic Feature/Description Parameter Name
Allowable Values
Default VHDL
Value Type
Notes:
1. The range C_BASEADDR to C_HIGHADDR is the address range for the XPS SPI IP Courthouse range is subject to restrictions
to accommodate the simple address decoding scheme that is employed: The size, C_HIGHADDR - C_BASEADDR + 1, must be
a power of two and must be at least 0x80 to accommodate all XPS SPI IP Core registers. However, a larger power of two may be
chosen to reduce decoding logic. C_BASEADDR must be aligned to a multiple of the range size.
2. No default value will be specified to insure that an actual value appropriate to the system is set. User must set the values.
3. Point to point bus topology is not allowed in this version of XPS SPI IP Core.
4. Burst to-from PLB is not supported in this version of XPS SPI IP Core.
5. C_SCK_RATIO = 2 is not supported when XPS SPI IP Core is configured as slave. So, user must take care in not configuring
C_SCK_RATIO = 2 while using XPS SPI IP Core as slave.
6. Please read the Precautions to be Taken while Assigning the C_SCK_RATIO Parameter section carefully while using this
parameter.
I/O Signals
The I/O signals are listed and described in Table 2.
Table 2: I/O Signal Descriptions
Port
Signal Name
Interface I/O
Initial
State
Description
System Signals
P1 SPLB_Clk
System
I
-
PLB clock
P2 SPLB_Rst
System
I
-
PLB reset, active high
P3 IP2INTC_Irpt
System O
0 Interrupt control signal from SPI
PLB Master Interface Signals
P4 PLB_ABus[0 : 31]
PLB
I
-
PLB address bus
P5 PLB_PAValid
PLB
I
-
PLB primary address valid
P6
PLB_masterID[0 :
C_SPLB_MID_WIDTH - 1]
PLB
I
-
PLB current master identifier
P7 PLB_RNW
PLB
I
-
PLB read not write
P8
PLB_BE[0 :
(C_SPLB_DWIDTH/8) - 1]
PLB
I
-
PLB byte enables
P9 PLB_size[0 : 3]
PLB
I
-
PLB size of requested transfer
P10 PLB_type[0 : 2]
PLB
I
-
PLB transfer type
P11
PLB_wrDBus[0 :
C_SPLB_DWIDTH - 1]
PLB
I
-
PLB write data bus
Unused PLB Master Interface Signals
P12 PLB_UABus[0 : 31]
PLB
I
-
PLB upper address bits
P13 PLB_SAValid
PLB
I
-
PLB secondary address valid
P14 PLB_rdPrim
PLB
I
-
PLB secondary to primary read request indicator
P15 PLB_wrPrim
PLB
I
-
PLB secondary to primary write request indicator
P16 PLB_abort
PLB
I
-
PLB abort bus request
P17 PLB_busLock
PLB
I
-
PLB bus lock
P18 PLB_MSize[0 : 1]
PLB
I
-
PLB data bus width indicator
DS570 June 22, 2011
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Product Specification