DS570 Datasheet, PDF (18/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Table 15: IP Interrupt Enable Register (IPIER) Description (C_BASEADDR + 0x28)
Bit(s)
Name
Access
Reset
Value
Description
0 - 22
Reserved
N/A
N/A Reserved
23
DRR_Not_Empty
R/W
DRR_Not_Empty.
’0’ = Disabled
’1’ = Enabled
Please note that setting of this bit is applicable only when the
’0’
C_FIFO_EXIST = 1 and the core is configured in slave mode.
If C_FIFO_EXIST = 0, setting of this bit wont affect. It means this bit
won’t be set in IPIER. So it is recommended to use this bit only in
C_FIFO_EXIST = 1 condition when the core is configured in slave
mode.
24 Slave_Select_Mode R/W
Slave_Select_Mode.
’0’ = Disabled
’1’ = Enabled
’0’
Please note that this bit is applicable only when the core is
configured in the slave mode. If in the master mode, this bit is set, it
won’t have effect on any logic. It is recommended to use this bit only
when the core is configured in slave mode.
25 Tx FIFO Half Empty R/W
Transmit FIFO Half Empty.
’0’ = Disabled
’1’ = Enabled
’0’
Please note that setting of this bit is applicable only when the
C_FIFO_EXIST = 1. If C_FIFO_EXIST = 0, setting of this bit wont
affect any logic. It means this bit wont be set in IPIER. So it is
recommended to use this bit only in C_FIFO_EXIST = 1 condition.
26
DRR Over-run
R/W
Receive FIFO Over-run.
’0’
’0’ = Disabled
’1’ = Enabled
Data Receive Register/FIFO Full.
27
DRR Full
R/W
’0’
’0’ = Disabled
’1’ = Enabled
28
DTR Under-run
R/W
Data Transmit FIFO Under-run.
’0’
’0’ = Disabled
’1’ = Enabled
Data Transmit Register/FIFO Empty.
29
DTR Empty
R/W
’0’
’0’ = Disabled
’1’ = Enabled
Slave Mode-Fault Error Flag.
30
Slave MODF
R/W
’0’
’0’ = Disabled
’1’ = Enabled
Mode-Fault Error Flag.
31
MODF
R/W
’0’
’0’ = Disabled
’1’ = Enabled
DS570 June 22, 2011
www.xilinx.com
18
Product Specification