DS570 Datasheet, PDF (6/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
Table 2: I/O Signal Descriptions (Cont’d)
Port
Signal Name
Interface I/O
Initial
State
Description
P19 PLB_lockErr
PLB
I
-
PLB lock error
P20 PLB_wrBurst
PLB
I
-
PLB burst write transfer
P21 PLB_rdBurst
PLB
I
-
PLB burst read transfer
P22 PLB_wrPendReq
PLB
I
-
PLB pending bus write request
P23 PLB_rdPendReq
PLB
I
-
PLB pending bus read request
P24 PLB_wrPendPri[0 : 1]
PLB
I
-
PLB pending write request priority
P25 PLB_rdPendPri[0 : 1]
PLB
I
-
PLB pending read request priority
P26 PLB_reqPri[0 : 1]
PLB
I
-
PLB current request priority
P27 PLB_TAttribute[0 : 15]
PLB
I
-
PLB transfer attribute
PLB Slave Interface Signals
P28 Sl_addrAck
PLB
O
0 Slave address acknowledge
P29 Sl_SSize[0 : 1]
PLB
O
0 Slave data bus size
P30 Sl_wait
PLB
O
0 Slave wait
P31 Sl_rearbitrate
PLB
O
0 Slave bus rearbitrate
P32 Sl_wrDAck
PLB
O
0 Slave write data acknowledge
P33 Sl_wrComp
PLB
O
0 Slave write transfer complete
P34
Sl_rdDBus[0 :
C_SPLB_DWIDTH - 1]
PLB
O
0
Slave read data bus
P35 Sl_rdDAck
PLB
O
0 Slave read data acknowledge
P36 Sl_rdComp
PLB
O
0 Slave read transfer complete
P37
Sl_MBusy[0:C_SPLB_
NUM_MASTERS - 1]
PLB
O
0
Slave busy
P38
Sl_MWrErr[0C_SPLB_
NUM_MASTERS - 1]
PLB
O
0
Slave write error
P39
Sl_MRdErr[0C_SPLB_
NUM_MASTERS - 1]
PLB
O
0
Slave read error
Unused PLB Slave Interface Signals
P40 Sl_wrBTerm
PLB
O
0 Slave terminate write burst transfer
P41 Sl_rdWdAddr[0 : 3]
PLB
O
0 Slave read word address
P42 Sl_rdBTerm
PLB
O
0 Slave terminate read burst transfer
Sl_MIRQ[0 :
P43 C_SPLB_NUM_MASTERS PLB
O
- 1]
0
Master interrupt request
SPI Interface Signals
P44 SCK_I
SPI
I
-
SPI bus clock input
P45 SCK_O
SPI
O
0 SPI bus clock output
SCK_T
P46
SPI
O
3-state enable for SPI bus clock.
1
Active low
P47 MOSI_I
SPI
I
-
Master output slave input
P48 MOSI_O
SPI
O
1 Master output slave input
DS570 June 22, 2011
www.xilinx.com
6
Product Specification