DS570 Datasheet, PDF (36/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately 70% and the
I/O utilization to approximately 80%. Using the default tool options and the slowest speed grade for the target
FPGA, the resulting target F_MAX numbers are shown in Table 21.
Table 21: XPS SPI IP Core System Performance
Target FPGA
S3A700 -4
Target F_MAX (MHz)
90
V4FX60 -10
100
V5LXT50 -1
120
V6LXT130-1
150
S6LXT45-2
100
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed value across
all systems.
Specification Exceptions
Exceptions from the Motorola M68HC11-Rev. 4.0 Reference Manual
1. A slave mode-fault -error interrupt is added to provide an interrupt if a SPI device is configured as a slave and
is selected when not enabled. A Slave_Mode_Select interrupt is added to indicate that the core is selected in the
slave mode when its SPISEL is asserted by master SPI.
2. In this design, the SPIDTR and SPIDRR registers have independent addresses. This is an exception to the
M68HC11 specification which calls for two registers to have the same address.
3. All SS signals are required to be routed between SPI devices internally to the FPGA. This is because toggling of
the SS signal is utilized in slaves to minimize FPGA resources.
4. Manual control of the SS signals is provided by setting bit(24) in the SPICR register. When the device is
configured as a master and is enabled and bit(24) of the SPICR register is set, the vector in the SPISSR register
is asserted. When this mode is enabled, multiple elements can be transferred without toggling the SS vector.
5. A control bit is provided to inhibit master transfers. This bit is effective in any master mode, but has main utility
in manual control of the SS signals.
6. In the M68HC11 implementation, the transmit register is transparent to the shift register which necessitates the
write collision error (WCOL) detection hardware. This is not implemented in this design.
7. The interrupt enable bit (SPIE) defined by the M68HC11 specifications which resides in the M68HC11 control
register has been moved to the IPIER register. In the position of the SPIE bit, there is a bit to select local master
loopback mode for testing.
8. An option is implemented in this FPGA design to implement FIFOs on both transmit and receive (Full Duplex
only) mode.
9. M68HC11 implementation supports only byte transfer. In this design either a byte, half-word or word transfer
can be configured via a generic C_NUM_TRANSFER_BITS.
10. The baud rate generator is specified by Motorola to be programmable via bits in the control register; however,
in this FPGA design the baud rate generator is programmable via parameters in the VHDL implementation.
Thus, in this implementation run time configuration of baud rate is not possible. Furthermore, in addition to the
ratios of 2, 4, 16 and 32, all integer multiples of 16 up to 2048 are allowed.
11. The XPS SPI IP Core is tested with Atmel AT45DB161D and ST Microelectronics M25P16 serial SPI slave
devices. These devices support the SPI mode 0 and mode 3. These devices have data valid time of 8 ns from the
falling edge of SCK. While operating with these devices at higher speed of 50 MHz (most of the instructions
DS570 June 22, 2011
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Product Specification