DS570 Datasheet, PDF (23/38 Pages) Xilinx, Inc – Supports full-duplex operation

LogiCORE IP XPS Serial Peripheral Interface (SPI) (v2.02a)
the clock’s idle state = high). Determination of whether the edge of interest is rising or falling edge depends on the
idle state of the clock (i.e. CPOL setting).
The clock phase (CPHA) bit can be set to select one of two different transfer formats. If CPHA = ’0’, data is valid on
the first SCK edge (rising or falling) after SS(N) has been asserted. If CPHA = ’1’, data is valid on the second SCK
edge (rising or falling) after SS(N) has asserted. For successful transfers the clock phase and polarity must be
identical for the master SPI device and the selected slave device.
The first SCK cycle begins with a transition of SCK signal from its idle state and this denotes the start of the data
transfer. Because the clock transition from idle denotes the start of a transfer, the M68HC11 specification notes that
SS(N) line may remain active low between successive transfers. The specification states that this format is useful in
systems with a single master and single slave. In the context of the M68HC11 specification, transmit data is placed
directly in the shift register upon a write to the transmit register. Consequently, it is the user’s responsibility to
insure that the data is properly loaded in the SPISSR register prior to the first SCK edge
The SS signal is toggled for all CPHA configurations and there is no support for SPISEL being held low. It is
required that all SS signals be routed between SPI devices internally to the FPGA. Toggling the SS signal reduces
FPGA resources.
The different transfer format are described in following sections.
CPHA Equals Zero Transfer Format
Figure 14 shows the timing diagram for an SPI data write cycle and Figure 15 shows the timing diagram for an SPI
data read cycle when CPHA = ’0’. The waveforms are shown for CPOL = ’0’, LSB First = ’0’, and the value of generic
C_SCK_RATIO = 4. All PLB and SPI signals will have same relation with respect to SPLB_Clk and SCK respectively.
X-Ref Target - Figure 14
0ns
100ns
200ns
300ns
400ns
Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
SPLB_Clk
PLB_ABus[0:31]
A0
PLB_PAValid
PLB_BE[0:3]
F
PLB_wrDBus[24:31]
Dt
PLB_RNW
Sl_addrAck
Sl_wrDack
Bus2ip_Data[0:7]
Dt
IP2Bus_WrAck
Transmit_Data[0:7]
Dt
transfer_start
SCK
MOSI
MISO
SS
SPISEL
Dt(0) Dt(1) Dt(2) Dt(3) Dt(4) Dt(5) Dt(6) Dt(7)
Dr(0) Dr(1) Dr(2) Dr(3) Dr(4) Dr(5) Dr(6) Dr(7) **
Legend:
A0: Address of Transmit_Data Register
Dt: Transmitted Data
Dr: Received Data
SCK is shown for CPOL = 0
**: Not defined, but normally MSB of character just received
DS570_14
Figure 14: Data Write Cycle on SPI Bus with CPHA = 0 and SPICR(24) = 0 for 8-bit data
DS570 June 22, 2011
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Product Specification