W89C841F Datasheet, PDF (9/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
4. PIN DESCRIPTION
PCI Interface
SIGNAL NAME
PCICLK
PCI_RSTB/
PHY_RSTB
AD[31:12]
AD[11]/
PWRDN
AD[10]/
INT
PIN TYP.
I
I
IO/TS
IO/TS/
I
IO/TS/
O
PIN NO.
117
116
123 − 127,
2 − 4, 7 − 9,
12 − 16, 29,
32 − 34
35
36
DESCRIPTION
PCI Clock Input
A. Normal and MAC mode
W89C841F supports PCI clock rate ranged from
25 MHz to 33 MHz continuously. All PCI signals
except PCI_RSTB and INTAB are referenced on
the rising edge of this clock.
B. PHYceiver mode
This pin should be pulled low.
PCI Hardware Reset Signal (Normal and MAC mode)
When asserted (active low), all PCI output pins of
W89C841F will be in high impedance state, and all
open drain signals will be floated.
The configurations inside W89C841F will be in its
initial state. This signal must be asserted for a period
of at least 10 PCI clocks to correctly take effect of a
reset on hardware.
PHYceiver Reset (PHYceiver Mode)
This pin is used as to reset PHYceiver.
PCI Multiplexed Address[31:12] and Data Bus[31:12]
During the first cycle that FRAMEB asserts, they act
as an address bus; on the other cycles, they are
switched to be a data bus.
PCI Multiplexed Address[11] and Data Bus[11]
(Normal and MAC mode)
Power Down Enable (PHYceiver Mode)
1: Power Saving.
0: Normal.
PCI Multiplexed Address[10] and Data Bus[10]
(Normal and MAC mode)
PHY Interrupt (PHYceiver Mode)
Output low that is asserted to indicate an active
interrupt event has occurred.
Publication Release Date: October 18, 2001
-9-
Revision A3