W89C841F Datasheet, PDF (32/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
The bit BROMRD (bit 27) and bit BROMWR (bit 26) of the register Dc0/DBRAR should not be set to 1
at the same time. In the case of both of the bit BROMRD and bit BROMWR are 1, it will not properly
initialize the read or the write operation for ROM device. The application program can check the
contents of the register Dc0/DBRAR to know if the read or write operation is already completed or not.
W89C841F will start the read or the write operation when the bit BROMRD or bit BROMWR are set to
high and will be reset automatically after the read/write operation is completed. For the write operation,
the software driver should not start up the next write data request until the bit BROMWR of
Dc0/DBRAR[26] is reset to 0 by W89C841F. For the read operation, the read data will be valid only if
the bit BROMRD of the register Dc0/DBRAR[27] is reset to 0 by W89C841F.
MII Management Function
W89C841F supports MII management function through register Dc8/DMMAR to access the MII
management registers of the internal PHYceiver (Normal mode) or external PHYceiver (MAC controller
mode). The following table lists the read and write access steps for MII management registers.
COMMAND
Read
Write
STEP
Set PHY address to bits PHYADD to default value 01h.
Set PHY register address to bits REGADD
Set MDIO read command to bit MDIORW
Set Start MDIO Read/write command to bit StartMDIORW
Waiting for read operation completed until bit StartMDIORW change to 0.
Read data from bits PHYData.
Set PHY address to bits PHYADD to default value 01h
Set PHY register address to bits REGADD
Set PHY data to bits PHYData
Set MDIO write command to bit MDIORW
Set Start MDIO Read/write command to bit StartMDIORW
6) Waiting for write operation completed until bit StartMDIORW change to 0.
System Resource Configuring
W89C841F will require the I/O space, memory space for function Cxx and Dxx registers and the
interrupt line to perform the communication between the network and the host.
In PCI/MiniPCI system, Cxx and Dxx registers can be mapped to either system I/O space or memory
space. The following table lists the relative mapping address in double word aligned.
Cxx Registers
Dxx Registers
I/O SPACE ADDRESS
00h − 3Ch
00h − FFh
MEMORY SPACE ADDRESS
000h − 03Ch
100h − 1FCh
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