W89C841F Datasheet, PDF (44/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
Fdc/FPMR0 Power Management Register 0, continued
BIT
18:16
15:8
7:0
ATTRIBUTE
R
R
R
BIT NAME
VERS
NXTPR
CAP_ID
DESCRIPTION
Version
Fixed at 010b. The W89C841F complies with Revision 1.1
of the PCI Power Management Interface Specification
Next Item Pointer
The value is dependent on the VPDEn loaded from
EEPROM to decide the W89C841F VPD capability link list
pointer.
If VPDEn = 1, NXTPR is equal to E4h.
If VPDEn = 0, NXTPR is equal to 00h.
Capability Identifier
Fixed to 01h. This linked list item is the PCI Power
Management registers.
Fe0/FPMR1 Power Management Register 1
The register provides the power management control, status and power consumption, dissipation data
of supported device power states.
BIT
31:24
23:16
15
ATTRIBUTE
R
R
Sticky bit,
R/WC
BIT NAME
PM_Data
---
PME_STS
DESCRIPTION
PM_Data
If bit PM_Data_En loaded from EEPROM is enabled,
PM_Data is used to report the state dependent data
requested by the D_Select field. The value is scaled by the
value reported by the D_Scale field. All of the PM_data will
be loaded from EEPROM after power on reset.
Reserved. Fixed at 0.
PME Status
This bit is set when the enabled Wake-up Frame detector
receives a Wake-up Frame or the enabled Magic Packet
detector receives a Magic Packet or the enabled Link Status
Change Detector detected a link status change independent
of the state of the PME_EN bit. When PME_STS and
PME_EN are set, W89C841F asserts PMEB.
Writing a 1 to this bit will clear it and cause W89C841F to
stop asserting a PMEB (if PME_En is enable). Writing a 0
has no effect.
This bit defaults to 0 if PMEB generation from D3cold is not
supported
If PMEB generation from D3cold is supported, then this bit
is sticky and must be explicitly cleared by the operating
system each time it is initially loaded.
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