W89C841F Datasheet, PDF (38/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
F08/FREV Device Revision Register
This register which is read-only shows class code, subclass code, interface code and revision ID.
BIT
31:24
23:16
15:8
7:0
ATTRIBUTE
R
R
R
R
BIT NAME
BC
SC
IC
REV
DESCRIPTION
Base Class Code
Loaded from EEPROM.
Subclass Code
Loaded from EEPROM.
Interface Code
Loaded from EEPROM.
Revision ID
Loaded from EEPROM.
F0C/FLT Latency Timer Register
This register specifies the latency timer of master bus in units of PCI bus clock.
BIT
31:24
23:16
15:8
7:0
ATTRIBUTE
R
R
R/W
R
BIT NAME
---
HT
LT
---
DESCRIPTION
Reserved, Fixed to 0.
Header Type, Fixed to 0.
Latency Timer
Specify, in units of PCI clocks, the latency timer value of
W89C841F. When W89C841F asserts FRAMEB, its latency
timer starts counting up. W89C841F will initiate the
transaction termination as soon as its GNTB de-asserted if
the timer expired before W89C841F de-asserts FRAMEB.
Reserved. Fixed at 0.
F10/FBIOAC Base I/O Address for Cxx Function Registers
This register is written by software after power-on reset to specify W89C841F base I/O address for
Cxx function registers access in the system.
BIT
31: 6
5:1
0
ATTRIBUTE
R/W
R
R
BIT NAME
BIOA
---
IO
DESCRIPTION
Base I/O Address
Written by power-on software to specify base I/O address
for Cxx function registers. W89C841F requires a 64 bytes
I/O space.
Reserved. Fixed at 0.
I/O Space Indicator
Fixed at 1.
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