W89C841F Datasheet, PDF (52/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C14/CISR Interrupt Status Register, continued
BIT
31:26
25:23
ATTRIBUTE
R
R
BIT NAME
---
BET
22:20
R
19:17
R
16
R
TPS
RPS
NIR
15
R
AIR
DESCRIPTION
Reserved. Fixed at 0.
Bus Error Type
The field indicates the error type of bus error and is valid
only when bit 13, bus error, is set. Assertion of these bits
does not generate interrupt.
The definition of bus error is as follows.
000 = Parity Error (Master Mode)
001 = Master Abort (Master Mode)
010 = Target Abort (Master Mode)
011 = Signaled System Error (Slave Mode)
100 = Data Parity Error (Slave Mode)
101 − 111 = Reserved
The initial state of this field after reset is 0.
Transmit Process State
This field indicates the transmit state. This field does not
generate interrupt.
Receive Process State
This field indicates the receive state. This field does not
generate interrupt.
Normal Interrupt Report
The normal interrupt report includes transmit completed
interrupt, transmit buffer unavailable interrupt, the
receive completed interrupt and the receive pause
packet interrupt.
The NIR is a logical OR result of the bits 0, 2, 6, 14 of
register C14/CISR. Only the bits corresponding to the
unmasked bits of C18/CIMR will affect this bit.
Abnormal Interrupt Report
The abnormal interrupt includes transmit process in idle
state interrupt, receive early interrupt, receive error
interrupt, transmit FIFO under-flow interrupt, receive
buffer unavailable interrupt, receive in idle state interrupt,
EEPROM Programming Fail Interrupt, transmit early
interrupt, timer expire interrupt, PHY Interrupt and the
bus error interrupt.
The AIR is a logical OR result of the bits 1, 3, 4, 5, 7, 8,
9, 10, 11, 12, 13 of register C14/CISR. Only these bits
corresponding to the unmasked bits of the C18/CIMR will
affect this bit.
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