W89C841F Datasheet, PDF (49/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C00/CBCR PCI Bus Control Register, continued
BIT
19:17
16
15:14
13:8
ATTRIBUTE
R
R/W
R/W
R/W
BIT NAME
---
PAE
CA
BL
DESCRIPTION
Reserved. Fixed at 0.
PCI Abort Enable
1: If bus error happened, TXDMA and RXDMA will halt.
Driver must reinitialized W89C841F. (default)
0: If bus error happened, TXDMA and RXDMA will not halt.
Wrong data will not be written into register of configuration
space, Cxx or Dxx.
Cache Alignment
CA defines the address boundary for the burst access to the
data transmission or reception. When the starting address
of the data burst access is not aligned, more specifically, the
starting address should be a multiple of some number such
as 4, 8 etc. W89C841F will have the first burst transfer that
causes that the next burst access will has the start address
aligned. After the first burst occurred, all other burst
operation are aligned with the configuration of CA
accordingly. The CA must be initialized with a non-zero
value after reset.
The alignment configuration is as following:
[00]
Reserved (default)
[01]
8 double word alignment
[10]
16 double word alignment
[11]
32 double word alignment
Burst Length
BL defines the maximum number of the double words that
can be transferred within one PCI burst transaction. The
burst length configuration is as following.
00h
Refer to CA
01h
1 double word
02h
2 double word
04h
4 double word
08h
8 double word
10h
16 double word
20h
32 double word
other
Reserved
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Publication Release Date: October 18, 2001
Revision A3