W89C841F Datasheet, PDF (33/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
In CardBus system, Cxx and Dxx registers can be mapped to either system I/O space or memory
space. But CIS data can be mapped to memory space only. The following table lists the relative
mapping address in double word.
Cxx Register
CIS Data
Dxx Register
I/O SPACE ADDRESS
00h − 3Ch
X
00h − FFh
MEMORY SPACE ADDRESS
000h − 03Ch
080h − 0FCh
100h − 1FCh
W89C841F uses only one interrupt pin INTAB. However, the interrupt line resource assignment is
determined by the system BIOS by writing the related data into the bits ILINE of register F3C/FIR[7:0].
Power Management Function
W89C841F supports power management function that is compliant with ACPI R1.0, PCI power
management R1.1 and Network Device Class Power management Reference specification V1.0a.
Power management state from D0, D1, D3(hot) is provided by W89C841F. But whether the D3(cold)
power management state is provided is dependent on the auxiliary power detected or not after power
on reset. Power management D2 is not supported by W89C841F.
PME context consists of the bit PME_EN of register Fe0/FPMR1[8] and bit PME_STS of register
Fe0/FPMR1[15]. If D3(cold) power management state is supported, PME context will be kept valid.
When PMEB is asserted, it must continue to drive the signal low until software explicitly either clears
the PME Status bit or clears the PME Enable bit.
Wake-On-LAN Function
If the power management function is enabled, 3 types of wake-up events can be accepted by
W89c841F to acknowledge driver that wake-up event has happened. These wake-up events are
defined as:
• Link status changed
• Magic Packet
• Wake-up frame
8. CONFIGURATION REGISTERS
The general attributes of the PCI configuration registers implemented in W89C841F are described as
the following.
1) Writes to the reserved configuration registers are treated as no-op. The bus access will complete
without affecting any data in W89C841F internal registers.
2) Read from the reserved or un-implemented registers will be returned 0 value.
3) SoftReset has no effect on the PCI configuration registers.
4) HardReset will clear the PCI configuration registers.
5) The implemented configuration registers support any byte enable combination access.
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Publication Release Date: October 18, 2001
Revision A3