W89C841F Datasheet, PDF (48/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
This table lists the initial state of each register in W89C841F after Stk_ResetB, PCI_ResetB,
D3toD0_ResetB and software reset.
CODE ABBR.
C00
CBCR
C04
CTSDR
C08
CRSDR
C0c
CRDLA
C10
CTDLA
C14
CISR
C18
CIMR
C1c
CNCR
C20
CFDCR
C24
CTDAR
C28
CTBAR
C2c
CRDAR
C30
CRBAR
C34
CMA0
C38
CMA1
C3c
CGTR
STK_RESETB, PCI_RESETB
D3TOD0_RESETB
0001_0010h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0130h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
SOFTWARE RESET
0001_0010h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0130h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
not affected
not affected
0000_0000h
The detail function and operation for each register in W89C841F will be described in the following
paragraph.
C00/CBCR PCI Bus Control Register
This register defines the configuration of PCI bus master.
BIT
31:22
21
20
ATTRIBUTE
R
R/W
R/W
BIT NAME
----
WAIT
DBE
DESCRIPTION
Reserved. Fixed to 0.
Wait State Insertion
When WAIT is set, W89C841F as a bus master executes
memory read/write with one wait state every data phase.
When WAIT is reset, W89C841F as a bus master executes
memory read/write with zero wait state every data phase.
Descriptor Big Endian Mode
When set, the descriptors will be handled in big endian
mode.
When reset, the descriptors will be treated in little endian
mode
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